Parameters |
Factory Lead Time |
6 Weeks |
Lifecycle Status |
ACTIVE (Last Updated: 5 days ago) |
Mount |
Surface Mount |
Mounting Type |
Surface Mount |
Package / Case |
20-TSSOP (0.173, 4.40mm Width) |
Number of Pins |
20 |
Weight |
76.997305mg |
Operating Temperature |
-40°C~85°C TA |
Packaging |
Cut Tape (CT) |
Series |
74LVTH |
JESD-609 Code |
e4 |
Pbfree Code |
yes |
Part Status |
Active |
Moisture Sensitivity Level (MSL) |
1 (Unlimited) |
Number of Terminations |
20 |
ECCN Code |
EAR99 |
Type |
D-Type |
Terminal Finish |
Nickel/Palladium/Gold (Ni/Pd/Au) |
Subcategory |
Bus Driver/Transceiver |
Packing Method |
TR |
Technology |
BICMOS |
Voltage - Supply |
2.7V~3.6V |
Terminal Position |
DUAL |
Terminal Form |
GULL WING |
Peak Reflow Temperature (Cel) |
260 |
Supply Voltage |
3.3V |
Terminal Pitch |
0.65mm |
Base Part Number |
74LVTH574 |
Function |
Standard |
Output Type |
Tri-State, Non-Inverted |
Operating Supply Voltage |
3.3V |
Number of Elements |
1 |
Polarity |
Non-Inverting |
Supply Voltage-Min (Vsup) |
2.7V |
Number of Circuits |
8 |
Load Capacitance |
50pF |
Number of Ports |
2 |
Output Current |
64mA |
Number of Bits |
8 |
Clock Frequency |
150MHz |
Propagation Delay |
5.9 ns |
Turn On Delay Time |
3 ns |
Family |
LVT |
Logic Function |
D-Type, Flip-Flop |
Current - Quiescent (Iq) |
190μA |
Current - Output High, Low |
32mA 64mA |
Max I(ol) |
0.064 A |
Max Propagation Delay @ V, Max CL |
4.5ns @ 3.3V, 50pF |
Prop. Delay@Nom-Sup |
4.5 ns |
Trigger Type |
Positive Edge |
Input Capacitance |
3pF |
Power Supply Current-Max (ICC) |
5mA |
Number of Output Lines |
3 |
Count Direction |
UNIDIRECTIONAL |
Clock Edge Trigger Type |
Positive Edge |
Height |
1.2mm |
Length |
6.5mm |
Width |
4.4mm |
Thickness |
1mm |
Radiation Hardening |
No |
RoHS Status |
ROHS3 Compliant |
Lead Free |
Lead Free |
SN74LVTH574PWR Overview
20-TSSOP (0.173, 4.40mm Width)is the packaging method. The Cut Tape (CT)package contains it. This output is configured with Tri-State, Non-Inverted. It is configured with a trigger that uses a value of Positive Edge. Surface Mountis positioned in the way of this electronic part. The supply voltage is set to 2.7V~3.6V. A temperature of -40°C~85°C TAis used in the operation. D-Typeis the type of this D latch. It belongs to the 74LVTHseries of FPGAs. You should not exceed 150MHzin its output frequency. The element count is 1 . There is a consumption of 190μAof quiescent energy. In 20terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. If you search by 74LVTH574, you will find similar parts. It is powered by a voltage of 3.3V . Its input capacitance is 3pF farads. It belongs to the family of electronic devices known as LVT. Electronic part Surface Mountis mounted in the way. Basically, it is designed with a set of 20 pins. This device exhibits a clock edge trigger type of Positive Edge. This part is included in Bus Driver/Transceiver. An electronic part designed with 8bits is used in this application. The supply voltage (Vsup) should be kept above 2.7V for normal operation. In order to achieve its superior flexibility, 8 circuits are used. Considering its reliability, this T flip flop is well suited for TR. The D flip flop is embedded with 2ports. In order to ensure high efficiency, the supply voltage should remain at 3.3V. It offers maximum design flexibility with its output current of 64mA. There are 3 output Lines, which generate the binary equivalent of the input line whose value is equal to “1” and are available to encode either a decimal or hexadecimal input pattern to typically a binary or “B. C. D” (binary coded decimal) output code.
SN74LVTH574PWR Features
Cut Tape (CT) package
74LVTH series
20 pins
8 Bits
SN74LVTH574PWR Applications
There are a lot of Texas Instruments SN74LVTH574PWR Flip Flops applications.
- Functionally equivalent to the MC10/100EL29
- Buffer registers
- Bus hold
- Convert a momentary switch to a toggle switch
- Dynamic threshold performance
- ATE
- ESD protection
- Set-reset capability
- Parallel data storage
- Registers