SN74LVTH273IPWREP
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 20-TSSOP (0.173, 4.40mm Width) |
| Number of Pins | 20 |
| Weight | 76.997305mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVTH |
| JESD-609 Code | e4 |
| Pbfree Code | no |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74LVTH273 |
| Function | Master Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Operating Supply Voltage | 3.3V |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Load Capacitance | 50pF |
| Output Current | 64mA |
| Number of Bits | 8 |
| Clock Frequency | 150MHz |
| Propagation Delay | 3.2 ns |
| Turn On Delay Time | 3.2 ns |
| Family | LVT |
| Current - Quiescent (Iq) | 190μA |
| Current - Output High, Low | 32mA 64mA |
| Max I(ol) | 0.064 A |
| Max Propagation Delay @ V, Max CL | 4.9ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 4.9 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Number of Output Lines | 8 |
| Clock Edge Trigger Type | Positive Edge |
| Length | 6.5mm |
| Width | 4.4mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Contains Lead |
SN74LVTH273IPWREP Overview
It is embeded in 20-TSSOP (0.173, 4.40mm Width) case. As part of the package Tape & Reel (TR), it is embedded. There is a Non-Invertedoutput configured with it. Positive Edgeis the trigger it is configured with. Surface Mountis in the way of this electric part. The supply voltage is set to 2.7V~3.6V. The operating temperature is -40°C~85°C TA. This D latch has the type D-Type. JK flip flop is a part of the 74LVTHseries of FPGAs. In order for it to function properly, its output frequency should not exceed 150MHz. A total of 1 elements are present. There is a consumption of 190μAof quiescent energy. Currently, there are 20 terminations. The 74LVTH273 family contains this object. The power supply voltage is 3.3V. A 4pFfarad input capacitance is provided by this T flip flop. Devices in the LVTfamily are electronic devices. There is an electronic part mounted in the way of Surface Mount. This board has 20 pins. This device has the clock edge trigger type of Positive Edge. This RS flip flops is a part number FF/Latches. There are 8bits in this flip flop. The maximal supply voltage (Vsup) reaches 3.6V. A normal operating voltage (Vsup) should remain above 2.7V. As a result of its reliable performance, this T flip flop is suitable for TR. For high efficiency, the supply voltage should be kept at 3.3V. Its output current of 64mAallows for maximum design flexibility. It is designed with 8 output lines.
SN74LVTH273IPWREP Features
Tape & Reel (TR) package
74LVTH series
20 pins
8 Bits
SN74LVTH273IPWREP Applications
There are a lot of Texas Instruments SN74LVTH273IPWREP Flip Flops applications.
- Asynchronous counter
- Common Clocks
- Parallel data storage
- Reduced system switching noise
- Computing
- Frequency Divider circuits
- Dynamic threshold performance
- Data storage
- Convert a momentary switch to a toggle switch
- Frequency Dividers