SN74LVC74APWG4
| Parameters | |
|---|---|
| Factory Lead Time | 6 Weeks |
| Lifecycle Status | ACTIVE (Last Updated: 1 week ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 14-TSSOP (0.173, 4.40mm Width) |
| Number of Pins | 14 |
| Weight | 57.209338mg |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Base Part Number | 74LVC74 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Number of Circuits | 2 |
| Load Capacitance | 50pF |
| Output Current | 24mA |
| Clock Frequency | 100MHz |
| Propagation Delay | 6 ns |
| Turn On Delay Time | 1 ns |
| Family | LVC/LCX/Z |
| Logic Function | AND, D-Type, Flip-Flop |
| Current - Quiescent (Iq) | 10μA |
| Current - Output High, Low | 24mA 24mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 5.2ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Number of Output Lines | 1 |
| Clock Edge Trigger Type | Positive Edge |
| Height | 1.2mm |
| Length | 5mm |
| Width | 4.4mm |
| Thickness | 1mm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74LVC74APWG4 Overview
In the form of 14-TSSOP (0.173, 4.40mm Width), it has been packaged. A package named Tubeincludes it. It is configured with Differentialas an output. JK flip flop uses Positive Edgeas the trigger. Surface Mountis occupied by this electronic component. It operates with a supply voltage of 1.65V~3.6V. In the operating environment, the temperature is -40°C~125°C TA. D-Typeis the type of this D latch. The 74LVCseries comprises this type of FPGA. You should not exceed 100MHzin its output frequency. It consumes 10μA of quiescent A total of 14terminations have been recorded. The 74LVC74 family contains it. A voltage of 1.8V is used as the power supply for this D latch. This JK flip flop has a 5pFfarad input capacitance. An electronic device belonging to the family LVC/LCX/Zcan be found here. The electronic part is mounted in the way of Surface Mount. The 14pins are designed into the board. Its clock edge trigger type is Positive Edge. There is a FF/Latchesbase part number assigned to the RS flip flops. The maximal supply voltage (Vsup) reaches 3.6V. 2 circuits are used to achieve its superior flexibility. In order for the device to operate, it requires 3.3V power supplies. Featuring the maximum design flexibility, it has an output current of 24mA . It has 1 output lines to operate.
SN74LVC74APWG4 Features
Tube package
74LVC series
14 pins
3.3V power supplies
SN74LVC74APWG4 Applications
There are a lot of Texas Instruments SN74LVC74APWG4 Flip Flops applications.
- Control circuits
- Consumer
- Supports Live Insertion
- CMOS Process
- Circuit Design
- Convert a momentary switch to a toggle switch
- Latch-up performance
- Test & Measurement
- Differential Individual
- Reduced system switching noise