SN74AUP1G74YZPR
| Parameters | |
|---|---|
| Factory Lead Time | 6 Weeks |
| Lifecycle Status | ACTIVE (Last Updated: 6 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-XFBGA, DSBGA |
| Number of Pins | 8 |
| Weight | 2.296311mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e1 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Tin/Silver/Copper (Sn/Ag/Cu) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.5mm |
| Base Part Number | 74AUP1G74 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Number of Circuits | 1 |
| Load Capacitance | 30pF |
| Output Current | 4mA |
| Number of Bits | 1 |
| Clock Frequency | 100MHz |
| Propagation Delay | 27 ns |
| Turn On Delay Time | 4 ns |
| Family | AUP/ULP/V |
| Logic Function | AND, D-Type |
| Current - Quiescent (Iq) | 500nA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 4mA 4mA |
| Max I(ol) | 0.004 A |
| Max Propagation Delay @ V, Max CL | 7ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 1.5pF |
| Power Supply Current-Max (ICC) | 0.0009mA |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 40000000Hz |
| Height | 500μm |
| Length | 1.25mm |
| Width | 2.25mm |
| Thickness | 310μm |
| Radiation Hardening | No |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74AUP1G74YZPR Overview
The flip flop is packaged in a case of 8-XFBGA, DSBGA. D flip flop is included in the Tape & Reel (TR)package. In the configuration, Differentialis used as the output. It is configured with a trigger that uses a value of Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 0.8V~3.6V volts. -40°C~85°C TAis the operating temperature. D-Typeis the type of this D latch. This type of FPGA is a part of the 74AUP series. It should not exceed 100MHzin terms of its output frequency. T flip flop consumes 500nA quiescent energy. There have been 8 terminations. The object belongs to the 74AUP1G74 family. It is powered from a supply voltage of 1.2V. Its input capacitance is 1.5pFfarads. AUP/ULP/Vis the family of this D flip flop. A part of the electronic system is mounted in the way of Surface Mount. This board has 8 pins. A Positive Edgeclock edge trigger is used in this device. There is a base part number FF/Latchesfor the RS flip flops. The flip flop is designed with 1bits. Vsup reaches its maximum value at 3.6V. In order to achieve its superior flexibility, 1 circuits are used. Compared to other similar T flip flops, this device offers reliable performance and is well suited for TR. As a result of its output current of 4mA, it is very flexible in terms of design.
SN74AUP1G74YZPR Features
Tape & Reel (TR) package
74AUP series
8 pins
1 Bits
SN74AUP1G74YZPR Applications
There are a lot of Texas Instruments SN74AUP1G74YZPR Flip Flops applications.
- Common Clocks
- Test & Measurement
- Storage Registers
- Synchronous counter
- Set-reset capability
- Buffered Clock
- Digital electronics systems
- Data storage
- Dynamic threshold performance
- Individual Asynchronous Resets