SN74AUC2G80DCUR
| Parameters | |
|---|---|
| Factory Lead Time | 6 Weeks |
| Lifecycle Status | ACTIVE (Last Updated: 3 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-VFSOP (0.091, 2.30mm Width) |
| Number of Pins | 8 |
| Weight | 9.610488mg |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUC |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| ECCN Code | EAR99 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 0.8V~2.7V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74AUC2G80 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Inverted |
| Polarity | Inverting |
| Number of Circuits | 2 |
| Clock Frequency | 275MHz |
| Propagation Delay | 2.4 ns |
| Turn On Delay Time | 5 ns |
| Family | AUC |
| Current - Quiescent (Iq) | 10μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 9mA 9mA |
| Max I(ol) | 0.009 A |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 1.8ns @ 2.5V, 30pF |
| Prop. Delay@Nom-Sup | 3.9 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 2.5pF |
| Number of Output Lines | 1 |
| Clock Edge Trigger Type | Positive Edge |
| Height | 900μm |
| Length | 2.3mm |
| Width | 2mm |
| Thickness | 850μm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN74AUC2G80DCUR Overview
It is embeded in 8-VFSOP (0.091, 2.30mm Width) case. You can find it in the Tape & Reel (TR)package. It is configured with Invertedas an output. It is configured with a trigger that uses a value of Positive Edge. It is mounted in the way of Surface Mount. A 0.8V~2.7Vsupply voltage is required for it to operate. It is at -40°C~85°C TAdegrees Celsius that the system is operating. This logic flip flop is classified as type D-Type. This type of FPGA is a part of the 74AUC series. You should not exceed 275MHzin the output frequency of the device. It consumes 10μA of quiescent current without being affected by external factors. There are 8 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. D latch belongs to the 74AUC2G80 family. The power supply voltage is 1.2V. JK flip flop input capacitance is 2.5pF farads. A device of this type belongs to the family of AUC. There is an electronic part mounted in the way of Surface Mount. It is designed with 8 pins. This device has the clock edge trigger type of Positive Edge. There is a FF/Latchesbase part number assigned to the RS flip flops. The superior flexibility of this product is achieved by using 2 circuits. As a result of its reliability, this D flip flop is ideally suited for TR. There are no output lines on the JK flip flop.
SN74AUC2G80DCUR Features
Tape & Reel (TR) package
74AUC series
8 pins
SN74AUC2G80DCUR Applications
There are a lot of Texas Instruments SN74AUC2G80DCUR Flip Flops applications.
- ESCC
- Divide a clock signal by 2 or 4
- Load Control
- Latch-up performance
- Frequency division
- Differential Individual
- Memory
- Common Clocks
- Event Detectors
- Matched Rise and Fall