SN74AS825ANT
| Parameters | |
|---|---|
| Mounting Type | Through Hole |
| Package / Case | 24-DIP (0.300, 7.62mm) |
| Surface Mount | NO |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tube |
| Series | 74AS |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 24 |
| Type | D-Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Additional Feature | WITH TRIPLE OUTPUT ENABLE; WITH CLEAR AND CLOCK ENABLE |
| Technology | TTL |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 5V |
| Terminal Pitch | 2.54mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDIP-T24 |
| Function | Master Reset |
| Qualification Status | COMMERCIAL |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Number of Ports | 2 |
| Family | AS |
| Current - Quiescent (Iq) | 73mA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 48mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 13ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Width | 7.62mm |
| RoHS Status | ROHS3 Compliant |
SN74AS825ANT Overview
It is embeded in 24-DIP (0.300, 7.62mm) case. There is an embedded version in the package Tube. T flip flop uses Tri-State, Non-Invertedas its output configuration. It is configured with a trigger that uses Positive Edge. Through Holeis occupied by this electronic component. The JK flip flop operates at 4.5V~5.5Vvolts. Temperature is set to 0°C~70°C TA. The type of this D latch is D-Type. It is a type of FPGA belonging to the 74AS series. A total of 1elements are present in it. There is 73mA quiescent consumption. A total of 24 terminations have been made. A voltage of 5V provides power to the D latch. A device of this type belongs to the family of AS. There is a 5.5Vmaximum supply voltage (Vsup). Normally, the supply voltage (Vsup) should be above 4.5V. A D flip flop with 2embedded ports is available. Additionally, you may refer to the D latch's additional WITH TRIPLE OUTPUT ENABLE; WITH CLEAR AND CLOCK ENABLE.
SN74AS825ANT Features
Tube package
74AS series
SN74AS825ANT Applications
There are a lot of Rochester Electronics, LLC SN74AS825ANT Flip Flops applications.
- Set-reset capability
- Computers
- Reduced system switching noise
- Synchronous counter
- ESD protection
- Consumer
- Data storage
- Bus hold
- Buffered Clock
- Memory