SN74ALVCH16820DLR
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 56-BSSOP (0.295, 7.50mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74ALVCH |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 56 |
| Type | D-Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.635mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G56 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Number of Ports | 2 |
| Clock Frequency | 150MHz |
| Family | ALVC/VCX/A |
| Current - Quiescent (Iq) | 40μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 10 |
| Max Propagation Delay @ V, Max CL | 4.8ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| Propagation Delay (tpd) | 5.9 ns |
| Height Seated (Max) | 2.79mm |
| Width | 7.49mm |
| RoHS Status | ROHS3 Compliant |
SN74ALVCH16820DLR Overview
In the form of 56-BSSOP (0.295, 7.50mm Width), it has been packaged. You can find it in the Tape & Reel (TR)package. T flip flop uses Tri-State, Non-Invertedas its output configuration. It is configured with a trigger that uses Positive Edge. Surface Mountis in the way of this electric part. A supply voltage of 1.65V~3.6V is required for operation. It is operating at a temperature of -40°C~85°C TA. Logic flip flops of this type are classified as D-Type. The FPGA belongs to the 74ALVCH series. Its output frequency should not exceed 150MHz Hz. A total of 1elements are present in it. During its operation, it consumes 40μA quiescent energy. There are 56 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. An input voltage of 1.8Vpowers the D latch. Input capacitance of this device is 3.5pF farads. The electronic device belongs to the ALVC/VCX/Afamily. It reaches 3.6Vwhen the maximum supply voltage (Vsup) is applied. The flip flop has 2embedded ports.
SN74ALVCH16820DLR Features
Tape & Reel (TR) package
74ALVCH series
SN74ALVCH16820DLR Applications
There are a lot of Rochester Electronics, LLC SN74ALVCH16820DLR Flip Flops applications.
- Bounce elimination switch
- Instrumentation
- Safety Clamp
- Matched Rise and Fall
- Single Down Count-Control Line
- Balanced Propagation Delays
- Consumer
- Count Modes
- Load Control
- Supports Live Insertion