SN65LVDS100DR
| Parameters | |
|---|---|
| Factory Lead Time | 8 Weeks |
| Lifecycle Status | ACTIVE (Last Updated: 4 days ago) |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 8 |
| Weight | 75.891673mg |
| Operating Temperature | -40°C~85°C |
| Packaging | Tape & Reel (TR) |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | Buffer, ReDriver |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | Line Driver or Receivers |
| Max Power Dissipation | 481mW |
| Technology | BIPOLAR |
| Voltage - Supply | 3V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Number of Functions | 1 |
| Supply Voltage | 3.3V |
| Base Part Number | 65LVDS100 |
| Output | LVDS |
| Pin Count | 8 |
| Operating Supply Voltage | 3.3V |
| Number of Elements | 1 |
| Operating Supply Current | 30mA |
| Power Dissipation | 481mW |
| Output Current | 12μA |
| Propagation Delay | 800 ps |
| Supply Current-Max | 0.033mA |
| Turn On Delay Time | 800 ps |
| Logic Function | Translator |
| Number of Inputs | 2 |
| Input | CML, LVDS, LVPECL |
| Driver Number of Bits | 1 |
| Receiver Number of Bits | 1 |
| Interface Standard | EIA-644-A; TIA-644-A |
| Data Rate (Max) | 2Gbps |
| Supply Voltage1-Nom | 3.3V |
| Delay Time | 470ps |
| Capacitance - Input | 0.6pF |
| Height | 1.75mm |
| Length | 4.9mm |
| Width | 3.91mm |
| Thickness | 1.58mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
SN65LVDS100DR Overview
A convenient transport package is provided in the power buffer of a 8-SOIC (0.154, 3.90mm Width).Power buffer ready in Tape & Reel (TR) packages.A universal mounting system for easy adaptation.On the topic of types, I would like to point out that this is a typical Buffer, ReDriver.3V~3.6V voltage is used to power this op amp buffer.Input of CML, LVDS, LVPECL is enabled by it.If you want to avoid malfunction, set the operating temperature to -40°C~85°C.In order to find more pin-to-pin solutions that will fit your specific needs, try typing "65LVDS100" in the search box.There are two 8 terminals on the op amp buffer and you can find them at the end of the op amp buffer.This material's peak reflow temperature is 260°C.Due to the 3.3V voltage supply, this splitter can handle a multitude of demanding tasks.From the 8 pins on the Power buffer, we can see the pinout of the Power buffer.The output is in LVDS.8 pins are included in it.In addition to the Surface Mount axis, it has a female hole for mounting to PCBs or other boards.In addition to the power buffer, other Line Driver or Receivers also play an important role.Using 30mA as a voltage, this power buffer operates.Operating voltage 3.3V is required for normal operation.Receiver uses 1-Bit technology.There is a maximum dissipation of 481mW of power from this splitter.A 1 element interface repeater signal such as this is used.Spliter output should be 12μA at the moment.
SN65LVDS100DR Features
A standard Line Driver or Receivers.
1-Bit receiver.
SN65LVDS100DR Applications
There are a lot of Texas Instruments SN65LVDS100DR Signal Buffers, Repeaters, Splitters applications.
- Protection Switching
- Servers
- Storage Area Networks
- Add/Drop Muxes
- DSLAMs
- Digital Crossconnects
- Data or Clock Signal Amplification
- Cable Repeaters
- Multidrop Buses
- Clock Distribution