PI74ALVCH16823A
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 56-TFSOP (0.240, 6.10mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74ALVCH |
| JESD-609 Code | e3 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 56 |
| Type | D-Type |
| Terminal Finish | Matte Tin (Sn) |
| Additional Feature | WITH CLEAR AND CLOCK ENABLE |
| Technology | CMOS |
| Voltage - Supply | 2.3V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 74ALVCH16823 |
| JESD-30 Code | R-PDSO-G56 |
| Function | Master Reset |
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Load Capacitance | 50pF |
| Number of Ports | 2 |
| Clock Frequency | 150MHz |
| Family | ALVC/VCX/A |
| Current - Quiescent (Iq) | 40μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 9 |
| Trigger Type | Positive Edge |
| Input Capacitance | 4.5pF |
| Propagation Delay (tpd) | 6.4 ns |
| Length | 14mm |
| Width | 6.1mm |
| RoHS Status | Non-RoHS Compliant |
PI74ALVCH16823A Overview
The flip flop is packaged in 56-TFSOP (0.240, 6.10mm Width). It is contained within the Tubepackage. T flip flop is configured with an output of Tri-State, Non-Inverted. The trigger it is configured with uses Positive Edge. There is an electrical part that is mounted in the way of Surface Mount. The JK flip flop operates at 2.3V~3.6Vvolts. In the operating environment, the temperature is -40°C~85°C TA. It is an electronic flip flop with the type D-Type. The FPGA belongs to the 74ALVCH series. Its output frequency should not exceed 150MHz Hz. The element count is 2 . This process consumes 40μA quiescents. Currently, there are 56 terminations. JK flip flop belongs to 74ALVCH16823 family. A voltage of 3.3V is used as the power supply for this D latch. The input capacitance of this T flip flop is 4.5pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. A device of this type belongs to the family of ALVC/VCX/A. As soon as 3.6Vis reached, Vsup reaches its maximum value. This flip flop has a total of 2ports. Furthermore, it has WITH CLEAR AND CLOCK ENABLEas a characteristic.
PI74ALVCH16823A Features
Tube package
74ALVCH series
PI74ALVCH16823A Applications
There are a lot of Diodes Incorporated PI74ALVCH16823A Flip Flops applications.
- Differential Individual
- Power down protection
- Shift Registers
- ESCC
- Clock pulse
- Pattern generators
- Single Down Count-Control Line
- Balanced Propagation Delays
- Memory
- Balanced 24 mA output drivers