MIMX8MQ5DVAJZAA
| Parameters | |
|---|---|
| Factory Lead Time | 15 Weeks |
| Package / Case | 621-FBGA, FCBGA |
| Operating Temperature | 0°C~95°C TJ |
| Packaging | Tray |
| Published | 2016 |
| Series | i.MX8MQ |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Peak Reflow Temperature (Cel) | 260 |
| Reach Compliance Code | compliant |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Speed | 1.5GHz |
| Core Processor | ARM® Cortex®-A53 |
| Ethernet | GbE |
| Number of Cores/Bus Width | 4 Core 32-Bit |
| Graphics Acceleration | Yes |
| RAM Controllers | DDR3L, DDR4, LPDDR4 |
| USB | USB 3.0 (2) |
| Additional Interfaces | EBI/EMI, I2C, PCIe, SPI, UART, uSDHC |
| Co-Processors/DSP | ARM® Cortex®-M4 |
| Security Features | ARM TZ, CAAM, HAB, RDC, RTC, SJC, SNVS |
| Display & Interface Controllers | eDP, HDMI, MIPI-CSI, MIPI-DSI |
| RoHS Status | RoHS Compliant |
MIMX8MQ5DVAJZAA Description
The i.MX 8M Dual / 8M QuadLite / 8M Quad processors represent NXP's latest market of connected streaming audio/video devices, scanning/imaging devices, and various devices requiring high-performance, low-power processors.
MIMX8MQ5DVAJZAA Features
Quad symmetric Cortex-A53 processors:
32 KB L1 Instruction Cache
32 KB L1 Data Cache
Support L1 cache RAMs protection with parity/ECC
Support of 64-bit Armv8-A architecture:
1 MB unified L2 cache
Support L2 cache RAMs protection with ECC
Frequency of 1.5 GHz
Arm Cortex-M4 core platform 16 KB L1 Instruction Cache
16 KB L1 Data Cache
256 KB tightly coupled memory (TCM)
Connectivity Two PCI Express Gen2 interfaces
Two USB 3.0/2.0 controllers with integrated PHY interfaces
Two Ultra Secure Digital Host Controller (uSDHC) interfaces
One Gigabit Ethernet controller with support for EEE, Ethernet AVB, and IEEE 1588
Four Universal Asynchronous Receiver/Transmitter (UART) modules
Four I2C modules
Three SPI modules