MC10EP35DTG
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-TSSOP, 8-MSOP (0.118, 3.00mm Width) |
| Number of Pins | 8 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Published | 2006 |
| Series | 10EP |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 8 |
| Type | JK Type |
| Terminal Finish | Tin (Sn) |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V |
| Subcategory | FF/Latches |
| Packing Method | RAIL |
| Technology | ECL |
| Voltage - Supply | -3V~-5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 40 |
| Base Part Number | 10EP35 |
| Function | Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | -5.2V |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Bits | 2 |
| Clock Frequency | 3GHz |
| Propagation Delay | 490 ps |
| Turn On Delay Time | 410 ps |
| Family | 10E |
| Logic Function | Flip-Flop, JK-Type |
| Halogen Free | Halogen Free |
| Prop. Delay@Nom-Sup | 0.575 ns |
| Trigger Type | Positive Edge |
| High Level Output Current | -50mA |
| Low Level Output Current | 50mA |
| Number of Output Lines | 1 |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 3000000000Hz |
| Length | 3mm |
| Width | 3mm |
| Radiation Hardening | No |
| RoHS Status | RoHS Compliant |
| Lead Free | Lead Free |
MC10EP35DTG Overview
As a result, it is packaged as 8-TSSOP, 8-MSOP (0.118, 3.00mm Width). The package Tubecontains it. T flip flop uses Differentialas its output configuration. The trigger it is configured with uses Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. A -3V~-5.5Vsupply voltage is required for it to operate. In the operating environment, the temperature is -40°C~85°C TA. JK Typedescribes this flip flop. The FPGA belongs to the 10EP series. You should not exceed 3GHzin its output frequency. There are 8 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. The 10EP35 family contains it. The D flip flop is powered by a voltage of 3.3V . Devices in the 10Efamily are electronic devices. There is an electronic part mounted in the way of Surface Mount. 8pins are included in its design. Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal. The clock edge trigger type of this device is Positive Edge. This part is included in FF/Latches. 2bits are used in its design. The maximal supply voltage (Vsup) reaches 5.5V. The supply voltage (Vsup) should be kept above 3V for normal operation. In view of its reliability, this D flip flop is a good fit for RAIL. A power supply of -5.2Vis required to operate it. The JK flip flop is with 1 output lines to operate. In addition, you can refer to the additinal NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V of the D latch. -50mAis set as the high level output current. There is 50mA output current at the low level.
MC10EP35DTG Features
Tube package
10EP series
8 pins
2 Bits
-5.2V power supplies
MC10EP35DTG Applications
There are a lot of ON Semiconductor MC10EP35DTG Flip Flops applications.
- ESD protection
- Computing
- Single Down Count-Control Line
- Single Up Count-Control Line
- Power down protection
- Consumer
- Storage registers
- Computers
- Modulo – n – counter
- Dynamic threshold performance