MC10EP35DR2
| Parameters | |
|---|---|
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 8 |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2008 |
| Series | 10EP |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | JK Type |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Additional Feature | NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | ECL |
| Voltage - Supply | -3V~-5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 240 |
| Supply Voltage | 3.3V |
| Reach Compliance Code | not_compliant |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 10EP35 |
| Function | Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | -5.2V |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Bits | 2 |
| Clock Frequency | 3GHz |
| Propagation Delay | 490 ps |
| Turn On Delay Time | 410 ps |
| Family | 10E |
| Logic Function | Flip-Flop |
| Prop. Delay@Nom-Sup | 0.575 ns |
| Trigger Type | Positive Edge |
| High Level Output Current | -50mA |
| Low Level Output Current | 50mA |
| Number of Output Lines | 1 |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 3000000000Hz |
| Length | 4.9mm |
| Width | 3.9mm |
| RoHS Status | Non-RoHS Compliant |
| Lead Free | Contains Lead |
MC10EP35DR2 Overview
In the form of 8-SOIC (0.154, 3.90mm Width), it has been packaged. You can find it in the Tape & Reel (TR)package. There is a Differentialoutput configured with it. There is a trigger configured with Positive Edge. This electronic part is mounted in the way of Surface Mount. A voltage of -3V~-5.5Vis used as the supply voltage. -40°C~85°C TAis the operating temperature. Logic flip flops of this type are classified as JK Type. This type of FPGA is a part of the 10EP series. A frequency of 3GHzshould be the maximum output frequency. There have been 8 terminations. It is a member of the 10EP35 family. A voltage of 3.3V is used to power it. In terms of electronic devices, this device belongs to the 10Efamily of devices. There is an electronic component mounted in the way of Surface Mount. With its 8pins, it is designed to work with most electronic flip flops. This device has Positive Edgeas its clock edge trigger type. It is part of the FF/Latchesbase part number family. This flip flop is designed with 2 Bits. Vsup reaches 5.5V, the maximal supply voltage. The supply voltage (Vsup) should be kept above 3V for normal operation. In light of its reliable performance, this T flip flop is well suited for TAPE AND REEL. The D latch runs on a voltage of -5.2V volts. The JK flip flop is with 1 output lines to operate. Furthermore, it has NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5Vas a characteristic. A high level output current of -50mAis set. A 50mAvalue is set for low-level output current.
MC10EP35DR2 Features
Tape & Reel (TR) package
10EP series
8 pins
2 Bits
-5.2V power supplies
MC10EP35DR2 Applications
There are a lot of ON Semiconductor MC10EP35DR2 Flip Flops applications.
- Count Modes
- Buffer registers
- ATE
- Differential Individual
- Frequency Dividers
- Single Up Count-Control Line
- Convert a momentary switch to a toggle switch
- Guaranteed simultaneous switching noise level
- Event Detectors
- Dynamic threshold performance