LPC1766FBD100
| Parameters | |
|---|---|
| Peripherals | DMA |
| Bit Size | 32 |
| Has ADC | YES |
| DMA Channels | YES |
| Number of Timers/Counters | 4 |
| Density | 2 Mb |
| CPU Family | ARM7 |
| Number of ADC Channels | 8 |
| ROM Programmability | FLASH |
| Number of PWM Channels | 6 |
| Number of GPIO | 70 |
| REACH SVHC | No SVHC |
| RoHS Status | RoHS Compliant |
| Package / Case | LQFP |
| Surface Mount | YES |
| Number of Pins | 100 |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Moisture Sensitivity Level (MSL) | 3 |
| Number of Terminations | 100 |
| Termination | SMD/SMT |
| Terminal Finish | Tin (Sn) |
| Max Operating Temperature | 85°C |
| Min Operating Temperature | -40°C |
| Subcategory | Microcontrollers |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.5mm |
| Frequency | 100MHz |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 100 |
| Qualification Status | Not Qualified |
| Power Supplies | 2.5/3.3V |
| Temperature Grade | INDUSTRIAL |
| Interface | CAN, I2C, SPI, SSP, UART |
| Max Supply Voltage | 3.6V |
| Min Supply Voltage | 2.4V |
| Memory Size | 256kB |
| Number of I/O | 70 |
| RAM Size | 64kB |
| uPs/uCs/Peripheral ICs Type | MICROCONTROLLER, RISC |
LPC1766FBD100 Decription
The LPC1766FBD100 is an embedded microcontroller for ARM Cortex-M3 applications that has a high level of integration and uses little power. A next-generation core, the ARM provides system improvements such improved debug tools and deeper support block integration. Up to 80 MHz of CPU frequency are supported by the LPC1766. The ARM Cortex-M3 CPU uses a Harvard architecture with a three-stage pipeline, independent local instruction and data buses, and a third bus for peripherals. Additionally, the inbuilt prefetch unit of the ARM Cortex-M3 CPU allows speculative branching. The LPC1766's peripheral complement consists of 4 UARTs, 2 CAN channels, 8-channel general-purpose DMA controller, Ethernet MAC, USB Device/Host/OTG interface, and kB of flash memory and kB of data memory. Two SSP controllers, three I2C interfaces, two inputs and two outputs on an I2S interface, an 8-channel 12-bit ADC, a 10-bit DAC, motor control PWM, a quadrature encoder interface, four general-purpose timers, six general-purpose outputs, an ultra-low power RTC with a separate battery supply, and up to 70 general-purpose I/O pins are all included. The ARM7-based LPC2366 microcontroller and the LPC1766 have pin compatibility.
There is a Memory Protection Unit (MPU) with support for eight regions. ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC) (NVIC). 256 kB of on-chip flash memory for programming. A better flash memory accelerator enables 80 MHz operating at high speed with no wait states. Using the on-chip boot loader software, in-system programming (ISP) and in-application programming (IAP) are possible. SRAM on the CPU with a local code/data channel for high-performance CPU access is included in the 64 kB on-chip SRAM. Two 16 kB SRAM blocks with distinct access pathways for improved throughput. Along with serving as general-purpose CPU instruction and data storage, these SRAM blocks can also be used as Ethernet, USB, and DMA memory.
LPC1766FBD100 Features
Package: QFP100
RoHS: Lead free / RoHS Compliant
LPC1766FBD100 Applications
Industrial
Personal electronics
Communications equipment