ISPLSI 5512VE-155LB388
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 388-BBGA |
| Surface Mount | YES |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tray |
| Published | 2002 |
| Series | ispLSI® 5000VE |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 388 |
| ECCN Code | EAR99 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| Additional Feature | YES |
| HTS Code | 8542.39.00.01 |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Supply Voltage | 3.3V |
| Terminal Pitch | 1.27mm |
| Base Part Number | ISPLSI 5512 |
| Pin Count | 388 |
| JESD-30 Code | S-PBGA-B388 |
| Qualification Status | Not Qualified |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 2.5/3.33.3V |
| Supply Voltage-Min (Vsup) | 3V |
| Programmable Type | In System Programmable |
| Number of I/O | 256 |
| Clock Frequency | 105MHz |
| Propagation Delay | 6.5 ns |
| Number of Gates | 24000 |
| Output Function | MACROCELL |
| Number of Macro Cells | 512 |
| JTAG BST | YES |
| Voltage Supply - Internal | 3V~3.6V |
| Delay Time tpd(1) Max | 6.5ns |
| Number of Logic Elements/Blocks | 16 |
| Height Seated (Max) | 3.25mm |
| Length | 35mm |
| Width | 35mm |
| RoHS Status | Non-RoHS Compliant |
ISPLSI 5512VE-155LB388 Overview
Currently, there are 512 macro cells, which are low-power cell sites (towers, antennas, masts) that serve as radio coverage.The item is packaged with 388-BBGA.As a result, it has 256 I/O ports programmed.It is programmed that device terminations will be 388 .BOTTOMis the terminal position of this electrical part.An electrical supply voltage of 3.3V is used to power it.It is a part of the family [0].Ideally, the chip should be packaged by Tray.A reliable operation is ensured by the operating temperature of [0].It is recommended that the chip be mounted by Surface Mount.It is a type of FPGA belonging to the ispLSI? 5000VE series.With 388pins programmed, the chip is ready to use.If you use this device, you will also find [0].There are related parts in [0].It is possible to construct digital circuits using 24000gates, which are devices that serve as building blocks.A logic element or block has 16elements.It runs on 2.5/3.33.3Vvolts of power.The maximal supply voltage (Vsup) reaches 3.6V.In order to operate properly, the supply voltage (Vsup) should be greater than 3V.The clock frequency should not exceed 105MHz.
ISPLSI 5512VE-155LB388 Features
388-BBGA package
256 I/Os
The operating temperature of 0°C~70°C TA
388 pin count
2.5/3.33.3V power supplies
ISPLSI 5512VE-155LB388 Applications
There are a lot of Lattice Semiconductor Corporation ISPLSI 5512VE-155LB388 CPLDs applications.
- Interface bridging
- Configurable Addressing of I/O Boards
- Custom shift registers
- Discrete logic functions
- STANDARD SERIAL INTERFACE UART
- ANALOG-TO-DIGITAL CONVERTOR (ADC)
- High speed graphics processing
- Address decoders
- SUPERVISORY FUNCTION (LVD AND WATCHDOG)
- I/O PORTS (MCU MODULE)