EPM7128AEFC100-10
| Parameters | |
|---|---|
| Factory Lead Time | 10 Weeks |
| Mount | Surface Mount |
| Package / Case | FBGA |
| Number of Pins | 100 |
| Published | 1998 |
| JESD-609 Code | e0 |
| Pbfree Code | no |
| Moisture Sensitivity Level (MSL) | 3 |
| Number of Terminations | 100 |
| ECCN Code | 3A991 |
| Terminal Finish | Tin/Lead (Sn63Pb37) |
| Max Operating Temperature | 70°C |
| Min Operating Temperature | 0°C |
| Additional Feature | YES |
| Subcategory | Programmable Logic Devices |
| Technology | CMOS |
| Terminal Position | BOTTOM |
| Terminal Form | BALL |
| Peak Reflow Temperature (Cel) | 235 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 1mm |
| Frequency | 125MHz |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Pin Count | 100 |
| Qualification Status | Not Qualified |
| Operating Supply Voltage | 3.3V |
| Temperature Grade | COMMERCIAL |
| Max Supply Voltage | 3.6V |
| Min Supply Voltage | 3V |
| Number of I/O | 84 |
| Memory Type | EEPROM |
| Propagation Delay | 10 ns |
| Turn On Delay Time | 10 ns |
| Frequency (Max) | 192.3MHz |
| Programmable Logic Type | EE PLD |
| Number of Gates | 2500 |
| Number of Programmable I/O | 84 |
| Number of Logic Blocks (LABs) | 8 |
| Speed Grade | 10 |
| Output Function | MACROCELL |
| Number of Macro Cells | 128 |
| JTAG BST | YES |
| In-System Programmable | YES |
| Height Seated (Max) | 1.7mm |
| Length | 11mm |
| Width | 11mm |
| RoHS Status | RoHS Compliant |
| Lead Free | Contains Lead |
EPM7128AEFC100-10 Overview
There are 128 macro cells, which are cells in a mobile phone network that provides radio coverage served by a high-power cell site (tower, antenna or mast).A FBGA package contains the item.The device is programmed with 84 I/O ports.There are 100 terminations programmed into the device.Its terminal position is BOTTOM.It is powered from a supply voltage of 3.3V.It is a part of the family [0].Chips are programmed with 100 pins.This device can also display [0].For digital circuits, there are 2500gates. These devices serve as building blocks.If high efficiency is desired, the supply voltage should be kept at [0].For storing data, it is recommended to use [0].In this case, it is mounted by Surface Mount.It is designed with 100 pins.This device operates at a voltage of 3.6Vas its maximum supply voltage.The minimal supply voltage is 3V.Programmable I/Os are counted up 84.This can be achieved at a frequency of 125MHz.It is recommended that the operating temperature exceeds 0°C.Ideally, the operating temperature should be below 70°C.The logic block consists of 8 l logic blocks (LABs).There should be a lower maximum frequency than 192.3MHz.This kind of FPGA is composed of EE PLD.
EPM7128AEFC100-10 Features
FBGA package
84 I/Os
100 pin count
100 pins
8 logic blocks (LABs)
EPM7128AEFC100-10 Applications
There are a lot of Altera EPM7128AEFC100-10 CPLDs applications.
- State machine design
- Custom state machines
- Power Meter SMPS
- PULSE WIDTH MODULATION (PWM)
- POWER-SAVING MODES
- Digital systems
- Address decoders
- SFP, QSFP, QSFP-DD, OSFP, Mini-SAS HD Port Management
- Reset swapping
- Synchronous or asynchronous mode