Parameters |
Mounting Type |
Surface Mount |
Package / Case |
16-SOIC (0.154, 3.90mm Width) |
Surface Mount |
YES |
Operating Temperature |
-55°C~125°C TA |
Packaging |
Tube |
Series |
74HCT |
Part Status |
Obsolete |
Moisture Sensitivity Level (MSL) |
1 (Unlimited) |
Number of Terminations |
16 |
Type |
D-Type |
Technology |
CMOS |
Voltage - Supply |
4.5V~5.5V |
Terminal Position |
DUAL |
Terminal Form |
GULL WING |
Supply Voltage |
5V |
Function |
Master Reset |
Qualification Status |
COMMERCIAL |
Output Type |
Non-Inverted |
Number of Elements |
1 |
Supply Voltage-Max (Vsup) |
5.5V |
Supply Voltage-Min (Vsup) |
4.5V |
Clock Frequency |
25MHz |
Family |
HCT |
Current - Quiescent (Iq) |
8μA |
Current - Output High, Low |
4mA 4mA |
Output Polarity |
TRUE |
Number of Bits per Element |
6 |
Max Propagation Delay @ V, Max CL |
40ns @ 4.5V, 50pF |
Trigger Type |
Positive Edge |
Input Capacitance |
10pF |
fmax-Min |
25 MHz |
RoHS Status |
Non-RoHS Compliant |
CD74HCT174M Overview
The flip flop is packaged in a case of 16-SOIC (0.154, 3.90mm Width). The Tubepackage contains it. T flip flop uses Non-Invertedas the output. This trigger uses the value Positive Edge. It is mounted in the way of Surface Mount. A 4.5V~5.5Vsupply voltage is required for it to operate. It is operating at -55°C~125°C TA. It is an electronic flip flop with the type D-Type. In terms of FPGAs, it belongs to the 74HCT series. Its output frequency should not exceed 25MHz Hz. In total, it contains 1 elements. There is 8μA quiescent consumption. A total of 16 terminations have been made. A voltage of 5V provides power to the D latch. A 10pFfarad input capacitance is provided by this T flip flop. It is a member of the HCTfamily of D flip flop. There is a 5.5Vmaximum supply voltage (Vsup). It is imperative that the supply voltage (Vsup) is maintained above 4.5Vin order to ensure normal operation.
CD74HCT174M Features
Tube package
74HCT series
CD74HCT174M Applications
There are a lot of Rochester Electronics, LLC CD74HCT174M Flip Flops applications.
- Synchronous counter
- Dynamic threshold performance
- Buffer registers
- High Performance Logic for test systems
- Computers
- Single Down Count-Control Line
- Individual Asynchronous Resets
- Set-reset capability
- Counters
- Balanced Propagation Delays