CD74HC107MT
| Parameters | |
|---|---|
| Factory Lead Time | 6 Weeks |
| Lifecycle Status | ACTIVE (Last Updated: 1 week ago) |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 14-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 14 |
| Weight | 129.387224mg |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74HC |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 14 |
| Termination | SMD/SMT |
| Type | JK Type |
| Subcategory | FF/Latches |
| Packing Method | TR |
| Technology | CMOS |
| Voltage - Supply | 2V~6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 4.5V |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74HC107 |
| Function | Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Circuits | 2 |
| Load Capacitance | 50pF |
| Output Current | 5.2mA |
| Clock Frequency | 60MHz |
| Propagation Delay | 170 ns |
| Quiescent Current | 4μA |
| Turn On Delay Time | 14 ns |
| Family | HC/UH |
| Logic Function | Flip-Flop, JK-Type |
| Current - Output High, Low | 5.2mA 5.2mA |
| Max I(ol) | 0.006 A |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 29ns @ 6V, 50pF |
| Trigger Type | Negative Edge |
| Input Capacitance | 10pF |
| Schmitt Trigger | No |
| Power Supply Current-Max (ICC) | 0.04mA |
| Clock Edge Trigger Type | Negative Edge |
| Height | 1.75mm |
| Length | 8.65mm |
| Width | 3.91mm |
| Thickness | 1.58mm |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
CD74HC107MT Overview
As a result, it is packaged as 14-SOIC (0.154, 3.90mm Width). There is an embedded version in the package Tape & Reel (TR). The output it is configured with uses Differential. JK flip flop uses Negative Edgeas the trigger. There is an electrical part that is mounted in the way of Surface Mount. The supply voltage is set to 2V~6V. A temperature of -55°C~125°C TAis considered to be the operating temperature. There is JK Type type of electronic flip flop associated with this device. It belongs to the 74HCseries of FPGAs. A frequency of 60MHzshould not be exceeded by its output. There are 14 terminations,The 74HC107 family contains this object. An input voltage of 4.5Vpowers the D latch. JK flip flop input capacitance is 10pF farads. Electronic devices of this type belong to the HC/UHfamily. Electronic part Surface Mountis mounted in the way. The electronic flip flop is designed with pins 14. This device has the clock edge trigger type of Negative Edge. This RS flip flops is a part number FF/Latches. The maximal supply voltage (Vsup) reaches 6V. Normally, the supply voltage (Vsup) should be above 2V. Despite its superior flexibility, it relies on 2 circuits to achieve it. Due to its reliability, this T flip flop is well suited for TR. In addition to its maximum design flexibility, the output current of the T flip flop is 5.2mA. This D latch consumes 4μA quiescent current at all.
CD74HC107MT Features
Tape & Reel (TR) package
74HC series
14 pins
CD74HC107MT Applications
There are a lot of Texas Instruments CD74HC107MT Flip Flops applications.
- Buffered Clock
- Matched Rise and Fall
- Count Modes
- Clock pulse
- Data transfer
- ATE
- Frequency division
- ESD protection
- Data storage
- Bus hold