CD74AC374E
| Parameters | |
|---|---|
| Mounting Type | Through Hole |
| Package / Case | 20-DIP (0.300, 7.62mm) |
| Surface Mount | NO |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Tube |
| Series | 74AC |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 20 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 1.5V~5.5V |
| Terminal Position | DUAL |
| Supply Voltage | 5V |
| JESD-30 Code | R-PDIP-T20 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Number of Ports | 2 |
| Clock Frequency | 125MHz |
| Family | AC |
| Current - Quiescent (Iq) | 8μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 10.8ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 10pF |
| RoHS Status | Non-RoHS Compliant |
CD74AC374E Overview
The item is packaged in 20-DIP (0.300, 7.62mm)cases. Package Tubeembeds it. The output it is configured with uses Tri-State, Non-Inverted. Positive Edgeis the trigger it is configured with. Through Holeis in the way of this electric part. With a supply voltage of 1.5V~5.5V volts, it operates. -55°C~125°C TAis the operating temperature. A flip flop of this type is classified as a D-Type. JK flip flop belongs to the 74ACseries of FPGAs. This D flip flop should not have a frequency greater than 125MHz. In total, it contains 1 elements. There is a consumption of 8μAof quiescent energy. There are 20 terminations,The D flip flop is powered by a voltage of 5V . A 10pFfarad input capacitance is provided by this T flip flop. This D flip flop belongs to the family of AC. Vsup reaches 5.5V, the maximal supply voltage. The D flip flop has no ports embedded.
CD74AC374E Features
Tube package
74AC series
CD74AC374E Applications
There are a lot of Rochester Electronics, LLC CD74AC374E Flip Flops applications.
- Patented noise
- Parallel data storage
- Single Down Count-Control Line
- Data transfer
- Matched Rise and Fall
- Guaranteed simultaneous switching noise level
- ATE
- Computing
- Computers
- 2 – Bit synchronous counter