CD4027BM
| Parameters | |
|---|---|
| Factory Lead Time | 6 Weeks |
| Lifecycle Status | ACTIVE (Last Updated: 3 days ago) |
| Contact Plating | Gold |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.154, 3.90mm Width) |
| Number of Pins | 16 |
| Weight | 141.690917mg |
| Operating Temperature | -55°C~125°C TA |
| Packaging | Tube |
| Series | 4000B |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| ECCN Code | EAR99 |
| Type | JK Type |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 3V~18V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Base Part Number | CD4027 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Polarity | Non-Inverting |
| Supply Voltage-Min (Vsup) | 3V |
| Number of Channels | 2 |
| Load Capacitance | 50pF |
| Output Current | 6.8mA |
| Clock Frequency | 24MHz |
| Propagation Delay | 300 ns |
| Quiescent Current | 20μA |
| Turn On Delay Time | 45 ns |
| Logic Function | AND, Flip-Flop, JK-Type |
| Current - Quiescent (Iq) | 4μA |
| Current - Output High, Low | 6.8mA 6.8mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 90ns @ 15V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Power Supply Current-Max (ICC) | 0.06mA |
| Clock Edge Trigger Type | Positive Edge |
| Max Frequency@Nom-Sup | 3500000Hz |
| Height | 1.75mm |
| Length | 9.9mm |
| Width | 3.91mm |
| Thickness | 1.58mm |
| Radiation Hardening | No |
| REACH SVHC | No SVHC |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
CD4027BM Overview
16-SOIC (0.154, 3.90mm Width)is the way it is packaged. D flip flop is included in the Tubepackage. T flip flop is configured with an output of Differential. This trigger is configured to use Positive Edge. This electronic part is mounted in the way of Surface Mount. The JK flip flop operates at 3V~18Vvolts. It is at -55°C~125°C TAdegrees Celsius that the system is operating. It is an electronic flip flop with the type JK Type. It belongs to the 4000Bseries of FPGAs. Its output frequency should not exceed 24MHz. During its operation, it consumes 4μA quiescent energy. Terminations are 16. This D latch belongs to the family of CD4027. A voltage of 5V is used to power it. The input capacitance of this T flip flop is 5pF farads, which is defined as the capacitance between the input terminals of an op amp with either input grounded. Surface Mount mounts this electronic component. The electronic flip flop is designed with pins 16. Edge triggering is a type of triggering that allows a circuit to become active at the positive edge or the negative edge of the clock signal. The clock edge trigger type of this device is Positive Edge. It is included in FF/Latches. The supply voltage (Vsup) should be kept above 3V for normal operation. With an output current of 6.8mA, it is possible to design the device in any way you want. This D latch consumes 20μA quiescent current at all. 2is the number of channels.
CD4027BM Features
Tube package
4000B series
16 pins
CD4027BM Applications
There are a lot of Texas Instruments CD4027BM Flip Flops applications.
- Modulo – n – counter
- Single Up Count-Control Line
- Test & Measurement
- Memory
- 2 – Bit synchronous counter
- Functionally equivalent to the MC10/100EL29
- Safety Clamp
- Count Modes
- Circuit Design
- Supports Live Insertion