74VCX16722MTDX
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 64-TFSOP (0.240, 6.10mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74VCX |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 2 (1 Year) |
| Number of Terminations | 64 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | CMOS |
| Voltage - Supply | 1.2V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G64 |
| Function | Standard |
| Qualification Status | COMMERCIAL |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Number of Ports | 2 |
| Clock Frequency | 250MHz |
| Family | ALVC/VCX/A |
| Current - Quiescent (Iq) | 20μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 22 |
| Max Propagation Delay @ V, Max CL | 3.6ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| Propagation Delay (tpd) | 9.2 ns |
| RoHS Status | ROHS3 Compliant |
74VCX16722MTDX Overview
The package is in the form of 64-TFSOP (0.240, 6.10mm Width). A package named Tape & Reel (TR)includes it. T flip flop is configured with an output of Tri-State, Non-Inverted. It is configured with the trigger Positive Edge. Surface Mountis in the way of this electric part. A voltage of 1.2V~3.6Vis used as the supply voltage. Currently, the operating temperature is -40°C~85°C TA. This logic flip flop is classified as type D-Type. It belongs to the 74VCXseries of FPGAs. Its output frequency should not exceed 250MHz. In total, it contains 1 elements. This process consumes 20μA quiescents. There are 64 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. The power supply voltage is 1.8V. JK flip flop input capacitance is 3.5pF farads. This D flip flop belongs to the family of ALVC/VCX/A. It reaches 3.6Vwhen the supply voltage is maximal (Vsup). A total of 2ports are embedded in the D flip flop.
74VCX16722MTDX Features
Tape & Reel (TR) package
74VCX series
74VCX16722MTDX Applications
There are a lot of Rochester Electronics, LLC 74VCX16722MTDX Flip Flops applications.
- ESCC
- Patented noise
- Digital electronics systems
- Single Up Count-Control Line
- Counters
- Consumer
- Latch
- Clock pulse
- Balanced Propagation Delays
- Cold spare funcion