74LVT374DB,118
| Parameters | |
|---|---|
| Packaging | Tape & Reel (TR) |
| Series | 74LVT |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVT374 |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Load Capacitance | 50pF |
| Number of Ports | 2 |
| Clock Frequency | 200MHz |
| Family | LVT |
| Current - Quiescent (Iq) | 190μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 32mA 64mA |
| Output Polarity | TRUE |
| Max I(ol) | 0.064 A |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 5.2ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Propagation Delay (tpd) | 5.5 ns |
| Height Seated (Max) | 2mm |
| Length | 7.2mm |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
| Mounting Type | Surface Mount |
| Package / Case | 20-SSOP (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
74LVT374DB,118 Overview
20-SSOP (0.209, 5.30mm Width)is the way it is packaged. It is included in the package Tape & Reel (TR). T flip flop uses Tri-State, Non-Invertedas the output. The trigger configured with it uses Positive Edge. There is an electrical part that is mounted in the way of Surface Mount. Powered by a 2.7V~3.6Vvolt supply, it operates as follows. Temperature is set to -40°C~85°C TA. It belongs to the type D-Typeof flip flops. The FPGA belongs to the 74LVT series. This D flip flop should not have a frequency greater than 200MHz. D latch consists of 1 elements. T flip flop consumes 190μA quiescent energy. In 20terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. The 74LVT374 family contains it. It is powered by a voltage of 3.3V . This T flip flop has a capacitance of 4pF farads at the input. This D flip flop belongs to the family of LVT. This device is part of the FF/Latchesbase part number family. It reaches 3.6Vwhen the maximum supply voltage (Vsup) is applied. A normal operating voltage (Vsup) should remain above 2.7V. This D flip flop is well suited for TAPE AND REEL based on its reliable performance. A power supply of 3.3Vis required to operate it. The D flip flop is embedded with 2ports.
74LVT374DB,118 Features
Tape & Reel (TR) package
74LVT series
3.3V power supplies
74LVT374DB,118 Applications
There are a lot of NXP USA Inc. 74LVT374DB,118 Flip Flops applications.
- Balanced Propagation Delays
- Data storage
- Computers
- Matched Rise and Fall
- Shift Registers
- Frequency Divider circuits
- Control circuits
- ATE
- EMI reduction circuitry
- Clock pulse