| Parameters |
| Load Capacitance |
50pF |
| Number of Ports |
2 |
| Number of Bits |
8 |
| Family |
LVC/LCX/Z |
| Output Characteristics |
3-STATE |
| Current - Output High, Low |
24mA 24mA |
| Logic Type |
D-Type Transparent Latch |
| Output Polarity |
TRUE |
| Prop. Delay@Nom-Sup |
5.5 ns |
| Independent Circuits |
2 |
| Delay Time - Propagation |
1.5ns |
| Width |
6.1mm |
| RoHS Status |
ROHS3 Compliant |
| Mounting Type |
Surface Mount |
| Package / Case |
48-TFSOP (0.240, 6.10mm Width) |
| Surface Mount |
YES |
| Operating Temperature |
-40°C~125°C |
| Packaging |
Tape & Reel (TR) |
| Series |
74LVCH |
| JESD-609 Code |
e4 |
| Part Status |
Obsolete |
| Moisture Sensitivity Level (MSL) |
2 (1 Year) |
| Number of Terminations |
48 |
| Terminal Finish |
NICKEL PALLADIUM GOLD |
| Subcategory |
FF/Latches |
| Packing Method |
TAPE AND REEL |
| Technology |
CMOS |
| Voltage - Supply |
1.2V~3.6V |
| Terminal Position |
DUAL |
| Terminal Form |
GULL WING |
| Peak Reflow Temperature (Cel) |
260 |
| Number of Functions |
2 |
| Supply Voltage |
2.7V |
| Terminal Pitch |
0.5mm |
| Time@Peak Reflow Temperature-Max (s) |
30 |
| Base Part Number |
74LVCH16373 |
| Pin Count |
48 |
| JESD-30 Code |
R-PDSO-G48 |
| Qualification Status |
Not Qualified |
| Output Type |
Tri-State |
| Circuit |
8:8 |
| Supply Voltage-Max (Vsup) |
3.6V |
| Power Supplies |
3.3V |
74LVCH16373ADGG:51 Overview
48-TFSOP (0.240, 6.10mm Width) contains it. Tape & Reel (TR) is the packaging method. There is a Tri-State output configured. The Logic type of this electrical device is D-Type Transparent Latch. The electronic component is mounted according to the Surface Mount method. A 1.2V~3.6V supply voltage is required to operate it. It is -40°C~125°C at the operating temperature. In the 74LVCH series, this FPGA is located. The design of this electronic part contains 8 bits. This device is designed with 48 terminations. 74LVCH16373 is its family. The device works with a voltage of 2.7V for its supply voltage. 48 pins are available on it. It is a member of the LVC/LCX/Z family of electronic devices. There are 2 ports, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. There is a subcategory of FF/Latches for this part. When Vsup reaches 3.6V, the maximal supply voltage is reached. There are 3.3V power supplies attached to it. As a result of its reliable performance, it is well suited for TAPE AND REEL.
74LVCH16373ADGG:51 Features
48-TFSOP (0.240, 6.10mm Width) package
74LVCH series
8 Bits
74LVCH16373 family
48 pin count
3.3V power supplies
74LVCH16373ADGG:51 Applications
There are a lot of NXP USA Inc. 74LVCH16373ADGG:51 Latches applications.
- BCD counting
- Parallel data storage
- Address register
- Pseudo-random code generators
- Frequency
- Motor Drives
- Relay
- Decade counting 7-segment decimal display
- Watches
- Parallel data synchronization