74LVC74APW/AUJ
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 14-TSSOP (0.173, 4.40mm Width) |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVC |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Type | D-Type |
| Voltage - Supply | 1.65V~3.6V |
| Base Part Number | 74LVC74 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Number of Elements | 2 |
| Clock Frequency | 250MHz |
| Current - Quiescent (Iq) | 10μA |
| Current - Output High, Low | 24mA 24mA |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 5.2ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| RoHS Status | ROHS3 Compliant |
74LVC74APW/AUJ Overview
14-TSSOP (0.173, 4.40mm Width)is the packaging method. There is an embedded version in the package Tape & Reel (TR). In the configuration, Differentialis used as the output. The trigger configured with it uses Positive Edge. There is an electric part mounted in the way of Surface Mount. The JK flip flop operates at a voltage of 1.65V~3.6V. A temperature of -40°C~125°C TAis considered to be the operating temperature. The type of this D latch is D-Type. The FPGA belongs to the 74LVC series. You should not exceed 250MHzin the output frequency of the device. D latch consists of 2 elements. There is a consumption of 10μAof quiescent energy. It is a member of the 74LVC74 family. Input capacitance of this device is 4pF farads.
74LVC74APW/AUJ Features
Tape & Reel (TR) package
74LVC series
74LVC74APW/AUJ Applications
There are a lot of NXP USA Inc. 74LVC74APW/AUJ Flip Flops applications.
- Load Control
- Dynamic threshold performance
- Frequency division
- CMOS Process
- Buffered Clock
- Frequency Divider circuits
- Single Down Count-Control Line
- Safety Clamp
- Matched Rise and Fall
- Data transfer