74LVC273BQ,115
| Parameters | |
|---|---|
| Factory Lead Time | 8 Weeks |
| Mounting Type | Surface Mount |
| Package / Case | 20-VFQFN Exposed Pad |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2006 |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag) |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | QUAD |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.7V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVC273 |
| JESD-30 Code | R-PQCC-N20 |
| Function | Master Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Clock Frequency | 230MHz |
| Family | LVC/LCX/Z |
| Current - Quiescent (Iq) | 10μA |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 8.2ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Length | 4.5mm |
| Width | 2.5mm |
| RoHS Status | ROHS3 Compliant |
74LVC273BQ,115 Overview
It is embeded in 20-VFQFN Exposed Pad case. It is contained within the Tape & Reel (TR)package. T flip flop uses Non-Invertedas its output configuration. JK flip flop uses Positive Edgeas the trigger. The electronic part is mounted in the way of Surface Mount. The JK flip flop operates with an input voltage of 1.65V~3.6V volts. It is operating at -40°C~125°C TA. A flip flop of this type is classified as a D-Type. JK flip flop belongs to the 74LVCseries of FPGAs. It should not exceed 230MHzin terms of its output frequency. The list contains 1 elements. It consumes 10μA of quiescent current without being affected by external factors. It has been determined that there have been 20 terminations. Members of the 74LVC273family make up this object. A voltage of 2.7V is used as the power supply for this D latch. A JK flip flop with a 5pFfarad input capacitance is used here. It is a member of the LVC/LCX/Zfamily of D flip flop. Vsup reaches its maximum value at 3.6V.
74LVC273BQ,115 Features
Tape & Reel (TR) package
74LVC series
74LVC273BQ,115 Applications
There are a lot of Nexperia USA Inc. 74LVC273BQ,115 Flip Flops applications.
- Asynchronous counter
- Storage registers
- Safety Clamp
- Buffer registers
- Storage Registers
- ESCC
- Pattern generators
- Clock pulse
- Divide a clock signal by 2 or 4
- Event Detectors