74LVC109D,118
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.154, 3.90mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2002 |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | JK Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVC109 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Load Capacitance | 50pF |
| Clock Frequency | 330MHz |
| Family | LVC/LCX/Z |
| Current - Quiescent (Iq) | 10μA |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | COMPLEMENTARY |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 6.8ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Propagation Delay (tpd) | 7.5 ns |
| Length | 9.9mm |
| Width | 3.9mm |
| RoHS Status | ROHS3 Compliant |
74LVC109D,118 Overview
The flip flop is packaged in a case of 16-SOIC (0.154, 3.90mm Width). A package named Tape & Reel (TR)includes it. T flip flop uses Differentialas its output configuration. It is configured with the trigger Positive Edge. Surface Mountmounts this electrical part. A voltage of 1.65V~3.6Vis used as the supply voltage. A temperature of -40°C~125°C TAis considered to be the operating temperature. The type of this D latch is JK Type. It is a type of FPGA belonging to the 74LVC series. You should not exceed 330MHzin its output frequency. The element count is 2 . T flip flop consumes 10μA quiescent energy. There are 16 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. D latch belongs to the 74LVC109 family. A voltage of 3.3V provides power to the D latch. A 5pFfarad input capacitance is provided by this T flip flop. In terms of electronic devices, this device belongs to the LVC/LCX/Zfamily of devices. As soon as Vsup reaches 3.6V, the maximum supply voltage is reached.
74LVC109D,118 Features
Tape & Reel (TR) package
74LVC series
74LVC109D,118 Applications
There are a lot of NXP USA Inc. 74LVC109D,118 Flip Flops applications.
- Shift Registers
- ESD protection
- Balanced Propagation Delays
- Shift registers
- Storage registers
- Storage Registers
- ESD performance
- Consumer
- Dynamic threshold performance
- Registers