74LV377PW,112
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-TSSOP (0.173, 4.40mm Width) |
| Supplier Device Package | 20-TSSOP |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Series | 74LV |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Type | D-Type |
| Voltage - Supply | 1V~3.6V |
| Function | Standard |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Clock Frequency | 70MHz |
| Current - Quiescent (Iq) | 20μA |
| Current - Output High, Low | 6mA 6mA |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 30ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| RoHS Status | ROHS3 Compliant |
74LV377PW,112 Overview
20-TSSOP (0.173, 4.40mm Width)is the way it is packaged. D flip flop is embedded in the Tube package. T flip flop is configured with an output of Non-Inverted. It is configured with the trigger Positive Edge. There is an electric part mounted in the way of Surface Mount. The supply voltage is set to 1V~3.6V. -40°C~125°C TAis the operating temperature. This logic flip flop is classified as type D-Type. It is a type of FPGA belonging to the 74LV series. A frequency of 70MHzshould be the maximum output frequency. D latch consists of 1 elements. There is a consumption of 20μAof quiescent energy. There is 3.5pF input capacitance for this T flip flop.
74LV377PW,112 Features
Tube package
74LV series
74LV377PW,112 Applications
There are a lot of Rochester Electronics, LLC 74LV377PW,112 Flip Flops applications.
- Buffer registers
- Shift registers
- Registers
- Cold spare funcion
- Event Detectors
- Matched Rise and Fall
- Buffered Clock
- Communications
- Frequency Divider circuits
- ESCC