74LV273D,118
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 1998 |
| Series | 74LV |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 1V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LV273 |
| JESD-30 Code | R-PDSO-G20 |
| Function | Master Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 1V |
| Load Capacitance | 50pF |
| Clock Frequency | 100MHz |
| Family | LV/LV-A/LVX/H |
| Current - Quiescent (Iq) | 160μA |
| Current - Output High, Low | 12mA 12mA |
| Output Polarity | TRUE |
| Max I(ol) | 0.006 A |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 16ns @ 5V, 50pF |
| Prop. Delay@Nom-Sup | 24 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| Propagation Delay (tpd) | 24 ns |
| fmax-Min | 20 MHz |
| Max Frequency@Nom-Sup | 20000000Hz |
| Height Seated (Max) | 2.65mm |
| Width | 7.5mm |
| RoHS Status | ROHS3 Compliant |
74LV273D,118 Overview
20-SOIC (0.295, 7.50mm Width)is the way it is packaged. You can find it in the Tape & Reel (TR)package. The output it is configured with uses Non-Inverted. It is configured with a trigger that uses a value of Positive Edge. It is mounted in the way of Surface Mount. The JK flip flop operates at 1V~5.5Vvolts. In the operating environment, the temperature is -40°C~125°C TA. It belongs to the type D-Typeof flip flops. The 74LVseries comprises this type of FPGA. There should be no greater frequency than 100MHzon its output. In total, there are 1 elements. This process consumes 160μA quiescents. A total of 20 terminations have been made. JK flip flop belongs to 74LV273 family. Power is supplied from a voltage of 3.3V volts. A 3.5pFfarad input capacitance is provided by this T flip flop. This D flip flop belongs to the family of LV/LV-A/LVX/H. The RS flip flops belongs to FF/Latches base part number. The maximal supply voltage (Vsup) reaches 5.5V. The supply voltage (Vsup) should be maintained above 1V for normal operation. A power supply of 3.3Vis required to operate it.
74LV273D,118 Features
Tape & Reel (TR) package
74LV series
3.3V power supplies
74LV273D,118 Applications
There are a lot of NXP USA Inc. 74LV273D,118 Flip Flops applications.
- Guaranteed simultaneous switching noise level
- Dynamic threshold performance
- Computers
- ESD performance
- Storage registers
- Reduced system switching noise
- Frequency Dividers
- Load Control
- Memory
- Storage Registers