74LV174DB,112
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 16-SSOP (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Published | 1998 |
| Series | 74LV |
| JESD-609 Code | e4 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Subcategory | FF/Latches |
| Technology | CMOS |
| Voltage - Supply | 1V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LV174 |
| Function | Master Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Power Supplies | 3.3V |
| Supply Voltage-Min (Vsup) | 1V |
| Load Capacitance | 50pF |
| Clock Frequency | 100MHz |
| Family | LV/LV-A/LVX/H |
| Current - Quiescent (Iq) | 160μA |
| Current - Output High, Low | 12mA 12mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 6 |
| Max Propagation Delay @ V, Max CL | 21ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| fmax-Min | 20 MHz |
| Max Frequency@Nom-Sup | 20000000Hz |
| Length | 5mm |
| Width | 4.4mm |
| RoHS Status | ROHS3 Compliant |
74LV174DB,112 Overview
16-SSOP (0.209, 5.30mm Width)is the packaging method. The package Tubecontains it. In the configuration, Non-Invertedis used as the output. It is configured with the trigger Positive Edge. Surface Mountis in the way of this electric part. With a supply voltage of 1V~5.5V volts, it operates. -40°C~125°C TAis the operating temperature. This logic flip flop is classified as type D-Type. It is a type of FPGA belonging to the 74LV series. You should not exceed 100MHzin the output frequency of the device. A total of 1elements are present in it. There is 160μA quiescent consumption. 16terminations have occurred. The 74LV174 family contains it. Power is supplied from a voltage of 3.3V volts. This JK flip flop has a 3.5pFfarad input capacitance. In this case, the D flip flop belongs to the LV/LV-A/LVX/Hfamily. The part you are looking for is included in FF/Latches. It reaches the maximum supply voltage (Vsup) at 5.5V. Normally, the supply voltage (Vsup) should be kept above 1V. A power supply of 3.3Vis required to operate it.
74LV174DB,112 Features
Tube package
74LV series
3.3V power supplies
74LV174DB,112 Applications
There are a lot of NXP USA Inc. 74LV174DB,112 Flip Flops applications.
- ESCC
- Convert a momentary switch to a toggle switch
- Power down protection
- Event Detectors
- CMOS Process
- Frequency division
- Digital electronics systems
- Bounce elimination switch
- Set-reset capability
- ESD performance