74HC273D,653
| Parameters | |
|---|---|
| Factory Lead Time | 4 Weeks |
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.295, 7.50mm Width) |
| Surface Mount | YES |
| Number of Pins | 20 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2011 |
| Series | 74HC |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Technology | CMOS |
| Voltage - Supply | 2V~6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74HC273 |
| Function | Master Reset |
| Qualification Status | Not Qualified |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Load Capacitance | 50pF |
| Output Current | 5.2mA |
| Clock Frequency | 122MHz |
| Family | HC/UH |
| Current - Quiescent (Iq) | 8μA |
| Current - Output High, Low | 5.2mA 5.2mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 26ns @ 6V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3.5pF |
| Propagation Delay (tpd) | 225 ns |
| fmax-Min | 24 MHz |
| Height Seated (Max) | 2.65mm |
| Width | 7.5mm |
| RoHS Status | ROHS3 Compliant |
74HC273D,653 Overview
The item is packaged in 20-SOIC (0.295, 7.50mm Width)cases. Package Tape & Reel (TR)embeds it. There is a Non-Invertedoutput configured with it. It is configured with a trigger that uses Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. A supply voltage of 2V~6V is required for operation. The operating temperature is -40°C~125°C TA. D-Typeis the type of this D latch. In this case, it is a type of FPGA belonging to the 74HC series. A frequency of 122MHzshould not be exceeded by its output. A total of 1elements are present in it. This process consumes 8μA quiescents. There have been 20 terminations. This D latch belongs to the family of 74HC273. It is powered by a voltage of 5V . A JK flip flop with a 3.5pFfarad input capacitance is used here. In terms of electronic devices, this device belongs to the HC/UHfamily of devices. There are 20pins on it. In this case, the maximum supply voltage (Vsup) reaches 6V. A normal operating voltage (Vsup) should remain above 2V. In addition to its maximum design flexibility, the output current of the T flip flop is 5.2mA.
74HC273D,653 Features
Tape & Reel (TR) package
74HC series
20 pins
74HC273D,653 Applications
There are a lot of Nexperia USA Inc. 74HC273D,653 Flip Flops applications.
- Divide a clock signal by 2 or 4
- Pattern generators
- Storage registers
- Data Synchronizers
- Individual Asynchronous Resets
- Set-reset capability
- Instrumentation
- Matched Rise and Fall
- Computers
- Guaranteed simultaneous switching noise level