74HC112D,652
| Parameters | |
|---|---|
| Factory Lead Time | 4 Weeks |
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.154, 3.90mm Width) |
| Surface Mount | YES |
| Number of Pins | 16 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tube |
| Published | 1998 |
| Series | 74HC |
| JESD-609 Code | e4 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | JK Type |
| Terminal Finish | Nickel/Palladium/Gold (Ni/Pd/Au) |
| Technology | CMOS |
| Voltage - Supply | 2V~6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 4.5V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74HC112 |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 6V |
| Supply Voltage-Min (Vsup) | 2V |
| Load Capacitance | 50pF |
| Clock Frequency | 71MHz |
| Family | HC/UH |
| Current - Quiescent (Iq) | 4μA |
| Current - Output High, Low | 5.2mA 5.2mA |
| Output Polarity | COMPLEMENTARY |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 30ns @ 6V, 50pF |
| Trigger Type | Negative Edge |
| Input Capacitance | 3.5pF |
| Length | 9.9mm |
| Width | 3.9mm |
| RoHS Status | ROHS3 Compliant |
74HC112D,652 Overview
As a result, it is packaged as 16-SOIC (0.154, 3.90mm Width). As part of the package Tube, it is embedded. As configured, the output uses Differential. This trigger uses the value Negative Edge. There is an electronic component mounted in the way of Surface Mount. Powered by a 2V~6Vvolt supply, it operates as follows. In this case, the operating temperature is -40°C~125°C TA. A flip flop of this type is classified as a JK Type. It is a type of FPGA belonging to the 74HC series. This D flip flop should not have a frequency greater than 71MHz. The element count is 2 . Despite external influences, it consumes 4μAof quiescent current. There are 16 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. Members of the 74HC112family make up this object. A voltage of 4.5V is used as the power supply for this D latch. This JK flip flop has a 3.5pFfarad input capacitance. Devices in the HC/UHfamily are electronic devices. This board is designed with 16pins on it. It reaches 6Vwhen the maximum supply voltage (Vsup) is applied. The supply voltage (Vsup) should be maintained above 2V for normal operation.
74HC112D,652 Features
Tube package
74HC series
16 pins
74HC112D,652 Applications
There are a lot of Nexperia USA Inc. 74HC112D,652 Flip Flops applications.
- Divide a clock signal by 2 or 4
- Balanced 24 mA output drivers
- Memory
- Data transfer
- Common Clocks
- Data storage
- ESD protection
- Buffer registers
- Convert a momentary switch to a toggle switch
- Circuit Design