74F112PC
| Parameters | |
|---|---|
| Mounting Type | Through Hole |
| Package / Case | 16-DIP (0.300, 7.62mm) |
| Surface Mount | NO |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tube |
| Series | 74F |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 16 |
| Type | JK Type |
| Terminal Finish | MATTE TIN |
| Technology | TTL |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | NOT APPLICABLE |
| Supply Voltage | 5V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT APPLICABLE |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Clock Frequency | 105MHz |
| Family | F/FAST |
| Current - Quiescent (Iq) | 19mA |
| Current - Output High, Low | 1mA 20mA |
| Output Polarity | COMPLEMENTARY |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 6.5ns @ 5V, 50pF |
| Trigger Type | Negative Edge |
| Propagation Delay (tpd) | 7.5 ns |
| fmax-Min | 80 MHz |
| Height Seated (Max) | 5.08mm |
| RoHS Status | ROHS3 Compliant |
74F112PC Overview
The flip flop is packaged in a case of 16-DIP (0.300, 7.62mm). Package Tubeembeds it. T flip flop is configured with an output of Differential. This trigger uses the value Negative Edge. It is mounted in the way of Through Hole. The supply voltage is set to 4.5V~5.5V. A temperature of 0°C~70°C TAis used in the operation. JK Typedescribes this flip flop. The 74Fseries comprises this type of FPGA. A frequency of 105MHzshould be the maximum output frequency. The list contains 2 elements. T flip flop consumes 19mA quiescent energy. There are 16 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line. Power is provided by a 5V supply. Electronic devices of this type belong to the F/FASTfamily. There is a 5.5Vmaximum supply voltage (Vsup). It is imperative that the supply voltage (Vsup) is maintained above 4.5Vin order to ensure normal operation.
74F112PC Features
Tube package
74F series
74F112PC Applications
There are a lot of Rochester Electronics, LLC 74F112PC Flip Flops applications.
- QML qualified product
- Buffered Clock
- Set-reset capability
- Bus hold
- Pattern generators
- Guaranteed simultaneous switching noise level
- ESD protection
- Frequency Dividers
- Memory
- Event Detectors