74AUP2G80GT,115
| Parameters | |
|---|---|
| Factory Lead Time | 13 Weeks |
| Mounting Type | Surface Mount |
| Package / Case | 8-XFDFN |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Published | 2010 |
| Series | 74AUP |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | D-Type |
| Terminal Finish | Tin (Sn) |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.2V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74AUP2G80 |
| JESD-30 Code | R-PDSO-N8 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Inverted |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 0.8V |
| Clock Frequency | 309MHz |
| Family | AUP/ULP/V |
| Current - Quiescent (Iq) | 500nA |
| Current - Output High, Low | 4mA 4mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 6.4ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 0.6pF |
| Height Seated (Max) | 0.5mm |
| RoHS Status | ROHS3 Compliant |
74AUP2G80GT,115 Overview
The item is packaged in 8-XFDFNcases. The package Tape & Reel (TR)contains it. T flip flop uses Invertedas its output configuration. Positive Edgeis the trigger it is configured with. Surface Mountis positioned in the way of this electronic part. With a supply voltage of 0.8V~3.6V volts, it operates. It is at -40°C~125°C TAdegrees Celsius that the system is operating. This logic flip flop is classified as type D-Type. It belongs to the 74AUPseries of FPGAs. Its output frequency should not exceed 309MHz. In total, it contains 2 elements. There is 500nA quiescent consumption. A total of 8terminations have been recorded. D latch belongs to the 74AUP2G80 family. Power is supplied from a voltage of 1.2V volts. JK flip flop input capacitance is 0.6pF farads. It is a member of the AUP/ULP/Vfamily of D flip flop. It reaches the maximum supply voltage (Vsup) at 3.6V. Normal operation requires a supply voltage (Vsup) above 0.8V.
74AUP2G80GT,115 Features
Tape & Reel (TR) package
74AUP series
74AUP2G80GT,115 Applications
There are a lot of Nexperia USA Inc. 74AUP2G80GT,115 Flip Flops applications.
- Convert a momentary switch to a toggle switch
- Differential Individual
- Individual Asynchronous Resets
- Control circuits
- ESCC
- Memory
- ATE
- Dynamic threshold performance
- Data storage
- Single Down Count-Control Line