74AUP1G79GS,132
| Parameters | |
|---|---|
| Factory Lead Time | 13 Weeks |
| Contact Plating | Tin |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 6-XFDFN |
| Number of Pins | 6 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| Type | D-Type |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 1.1V |
| Terminal Pitch | 0.35mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74AUP1G79 |
| Function | Standard |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Min (Vsup) | 0.8V |
| Number of Bits | 1 |
| Clock Frequency | 309MHz |
| Propagation Delay | 14.2 ns |
| Quiescent Current | 500nA |
| Turn On Delay Time | 2 ns |
| Family | AUP/ULP/V |
| Current - Output High, Low | 4mA 4mA |
| Max Propagation Delay @ V, Max CL | 5.8ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 0.8pF |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 0.35mm |
| RoHS Status | ROHS3 Compliant |
74AUP1G79GS,132 Overview
It is packaged in the way of 6-XFDFN. You can find it in the Tape & Reel (TR)package. In the configuration, Non-Invertedis used as the output. JK flip flop uses Positive Edgeas the trigger. Surface Mountis positioned in the way of this electronic part. The supply voltage is set to 0.8V~3.6V. In the operating environment, the temperature is -40°C~125°C TA. D-Typeis the type of this D latch. In FPGA terms, D flip flop is a type of 74AUPseries FPGA. A frequency of 309MHzshould be the maximum output frequency. In total, there are 1 elements. A total of 6 terminations have been made. The 74AUP1G79family includes it. A voltage of 1.1V is used as the power supply for this D latch. Its input capacitance is 0.8pFfarads. A device of this type belongs to the family of AUP/ULP/V. There is an electronic component mounted in the way of Surface Mount. Basically, it is designed with a set of 6 pins. In this device, the clock edge trigger type is Positive Edge. There are 1bits in its design. Normal operation requires a supply voltage (Vsup) above 0.8V. There is a consumption of 500nAof quiescent current from it.
74AUP1G79GS,132 Features
Tape & Reel (TR) package
74AUP series
6 pins
1 Bits
74AUP1G79GS,132 Applications
There are a lot of Nexperia USA Inc. 74AUP1G79GS,132 Flip Flops applications.
- Reduced system switching noise
- Memory
- Safety Clamp
- Differential Individual
- Digital electronics systems
- Parallel data storage
- Balanced 24 mA output drivers
- Data transfer
- Frequency Divider circuits
- Asynchronous counter