74AUP1G74GS,115
| Parameters | |
|---|---|
| Factory Lead Time | 13 Weeks |
| Mount | Surface Mount |
| Mounting Type | Surface Mount |
| Package / Case | 8-XFDFN |
| Number of Pins | 8 |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74AUP |
| JESD-609 Code | e3 |
| Part Status | Active |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 8 |
| Type | D-Type |
| Terminal Finish | Tin (Sn) |
| Technology | CMOS |
| Voltage - Supply | 0.8V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | NO LEAD |
| Peak Reflow Temperature (Cel) | NOT SPECIFIED |
| Supply Voltage | 1.1V |
| Terminal Pitch | 0.35mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Base Part Number | 74AUP1G74 |
| Function | Set(Preset) and Reset |
| Output Type | Differential |
| Number of Elements | 1 |
| Polarity | Non-Inverting |
| Supply Voltage-Max (Vsup) | 3.6V |
| Number of Bits | 1 |
| Clock Frequency | 315MHz |
| Propagation Delay | 14.2 ns |
| Quiescent Current | 500nA |
| Turn On Delay Time | 2.2 ns |
| Family | AUP/ULP/V |
| Logic Function | AND, D-Type |
| Current - Output High, Low | 4mA 4mA |
| Max Propagation Delay @ V, Max CL | 5.8ns @ 3.3V, 30pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 0.6pF |
| Clock Edge Trigger Type | Positive Edge |
| Height Seated (Max) | 0.35mm |
| RoHS Status | ROHS3 Compliant |
| Lead Free | Lead Free |
74AUP1G74GS,115 Overview
It is packaged in the way of 8-XFDFN. The package Tape & Reel (TR)contains it. T flip flop uses Differentialas the output. It is configured with a trigger that uses Positive Edge. It is mounted in the way of Surface Mount. The JK flip flop operates at a voltage of 0.8V~3.6V. -40°C~125°C TAis the operating temperature. Logic flip flops of this type are classified as D-Type. JK flip flop belongs to the 74AUPseries of FPGAs. Its output frequency should not exceed 315MHz. In total, there are 1 elements. In 8terminations, a transmission line is terminated with a JK flip flop that matches its characteristic impedance. This D latch belongs to the family of 74AUP1G74. The power supply voltage is 1.1V. JK flip flop input capacitance is 0.6pF farads. Devices in the AUP/ULP/Vfamily are electronic devices. There is an electronic part that is mounted in the way of Surface Mount. It is designed with 8 pins. There is a clock edge trigger type of Positive Edgeon this device. An electronic part designed with 1bits is used in this application. In this case, the maximum supply voltage (Vsup) reaches 3.6V. In terms of quiescent current, it consumes 500nA .
74AUP1G74GS,115 Features
Tape & Reel (TR) package
74AUP series
8 pins
1 Bits
74AUP1G74GS,115 Applications
There are a lot of Nexperia USA Inc. 74AUP1G74GS,115 Flip Flops applications.
- Asynchronous counter
- Individual Asynchronous Resets
- Single Up Count-Control Line
- Cold spare funcion
- Test & Measurement
- ESD performance
- ATE
- Divide a clock signal by 2 or 4
- Memory
- Matched Rise and Fall