74ALVT16823DGG,112
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 56-TFSOP (0.240, 6.10mm Width) |
| Supplier Device Package | 56-TSSOP |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74ALVT |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Type | D-Type |
| Voltage - Supply | 2.3V~2.7V 3V~3.6V |
| Function | Master Reset |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 2 |
| Clock Frequency | 250MHz |
| Current - Quiescent (Iq) | 100μA |
| Current - Output High, Low | 8mA 24mA; 32mA 64mA |
| Number of Bits per Element | 9 |
| Max Propagation Delay @ V, Max CL | 3.1ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3pF |
| RoHS Status | ROHS3 Compliant |
74ALVT16823DGG,112 Overview
As a result, it is packaged as 56-TFSOP (0.240, 6.10mm Width). A package named Tubeincludes it. T flip flop is configured with an output of Tri-State, Non-Inverted. This trigger is configured to use Positive Edge. Surface Mountmounts this electrical part. A 2.3V~2.7V 3V~3.6Vsupply voltage is required for it to operate. -40°C~85°C TAis the operating temperature. A flip flop of this type is classified as a D-Type. This type of FPGA is a part of the 74ALVT series. It should not exceed 250MHzin its output frequency. A total of 2 elements are present. During its operation, it consumes 100μA quiescent energy. JK flip flop input capacitance is 3pF farads.
74ALVT16823DGG,112 Features
Tube package
74ALVT series
74ALVT16823DGG,112 Applications
There are a lot of Rochester Electronics, LLC 74ALVT16823DGG,112 Flip Flops applications.
- ESD protection
- Balanced Propagation Delays
- Functionally equivalent to the MC10/100EL29
- ESD performance
- Circuit Design
- Storage Registers
- Frequency division
- 2 – Bit synchronous counter
- Computers
- Frequency Divider circuits