74ACTQ374QSC
| Parameters | |
|---|---|
| Terminal Finish | MATTE TIN |
| Technology | CMOS |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Terminal Pitch | 0.635mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Number of Ports | 2 |
| Clock Frequency | 85MHz |
| Family | ACT |
| Current - Quiescent (Iq) | 40μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 9ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4.5pF |
| Propagation Delay (tpd) | 9.5 ns |
| RoHS Status | ROHS3 Compliant |
| Mounting Type | Surface Mount |
| Package / Case | 20-LSSOP (0.154, 3.90mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74ACTQ |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
74ACTQ374QSC Overview
20-LSSOP (0.154, 3.90mm Width)is the way it is packaged. There is an embedded version in the package Tube. It is configured with Tri-State, Non-Invertedas an output. It is configured with a trigger that uses a value of Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. Powered by a 4.5V~5.5Vvolt supply, it operates as follows. A temperature of -40°C~85°C TAis used in the operation. There is D-Type type of electronic flip flop associated with this device. The FPGA belongs to the 74ACTQ series. A frequency of 85MHzshould be the maximum output frequency. The element count is 1 . As a result, it consumes 40μA of quiescent current without being affected by external factors. There have been 20 terminations. An input voltage of 5Vpowers the D latch. The input capacitance of this JK flip flopis 4.5pF farads. ACTis the family of this D flip flop. The maximal supply voltage (Vsup) reaches 5.5V. If you want to maintain normal operation, you should keep the supply voltage (Vsup) above 4.5V. This D flip flop is equipped with 0 ports.
74ACTQ374QSC Features
Tube package
74ACTQ series
74ACTQ374QSC Applications
There are a lot of Rochester Electronics, LLC 74ACTQ374QSC Flip Flops applications.
- Modulo – n – counter
- Computing
- Single Up Count-Control Line
- Storage registers
- Matched Rise and Fall
- Guaranteed simultaneous switching noise level
- Safety Clamp
- Event Detectors
- Digital electronics systems
- Clock pulse