74ACTQ16374MTD
| Parameters | |
|---|---|
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | CMOS |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Terminal Pitch | 0.5mm |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Function | Standard |
| Qualification Status | COMMERCIAL |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Number of Ports | 2 |
| Clock Frequency | 71MHz |
| Family | ACT |
| Current - Quiescent (Iq) | 80μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 7.9ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4.5pF |
| Width | 6.1mm |
| RoHS Status | ROHS3 Compliant |
| Mounting Type | Surface Mount |
| Package / Case | 48-TFSOP (0.240, 6.10mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74ACTQ |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 2 (1 Year) |
| Number of Terminations | 48 |
74ACTQ16374MTD Overview
It is packaged in the way of 48-TFSOP (0.240, 6.10mm Width). A package named Tubeincludes it. T flip flop is configured with an output of Tri-State, Non-Inverted. JK flip flop uses Positive Edgeas the trigger. Surface Mountis occupied by this electronic component. A voltage of 4.5V~5.5Vis used as the supply voltage. Currently, the operating temperature is -40°C~85°C TA. D-Typedescribes this flip flop. JK flip flop is a part of the 74ACTQseries of FPGAs. You should not exceed 71MHzin the output frequency of the device. A total of 2 elements are present. It consumes 80μA of quiescent It has been determined that there have been 48 terminations. Power is provided by a 5V supply. A 4.5pFfarad input capacitance is provided by this T flip flop. It is a member of the ACTfamily of D flip flop. It reaches the maximum supply voltage (Vsup) at 5.5V. The supply voltage (Vsup) should be kept above 4.5V for normal operation. There are 2 ports embedded in the flip flops.
74ACTQ16374MTD Features
Tube package
74ACTQ series
74ACTQ16374MTD Applications
There are a lot of Rochester Electronics, LLC 74ACTQ16374MTD Flip Flops applications.
- Data storage
- ATE
- Shift Registers
- Test & Measurement
- Communications
- Digital electronics systems
- Balanced Propagation Delays
- Matched Rise and Fall
- Event Detectors
- QML qualified product