74ACT273SJX
| Parameters | |
|---|---|
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | CMOS |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Master Reset |
| Qualification Status | COMMERCIAL |
| Output Type | Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Clock Frequency | 189MHz |
| Family | ACT |
| Current - Quiescent (Iq) | 40μA |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 8.5ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4.5pF |
| Propagation Delay (tpd) | 9 ns |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
| Mounting Type | Surface Mount |
| Package / Case | 20-SOIC (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74ACT |
74ACT273SJX Overview
The item is packaged in 20-SOIC (0.209, 5.30mm Width)cases. It is included in the package Tape & Reel (TR). As configured, the output uses Non-Inverted. The trigger it is configured with uses Positive Edge. This electronic part is mounted in the way of Surface Mount. A 4.5V~5.5Vsupply voltage is required for it to operate. In this case, the operating temperature is -40°C~85°C TA. Logic flip flops of this type are classified as D-Type. It belongs to the 74ACTseries of FPGAs. This D flip flop should not have a frequency greater than 189MHz. D latch consists of 1 elements. During its operation, it consumes 40μA quiescent energy. There are 20 terminations,A voltage of 5V provides power to the D latch. A 4.5pFfarad input capacitance is provided by this T flip flop. In this case, the D flip flop belongs to the ACTfamily. 5.5Vis the maximum supply voltage (Vsup). Normal operation requires a supply voltage (Vsup) above 4.5V.
74ACT273SJX Features
Tape & Reel (TR) package
74ACT series
74ACT273SJX Applications
There are a lot of Rochester Electronics, LLC 74ACT273SJX Flip Flops applications.
- Data storage
- Shift Registers
- Load Control
- Synchronous counter
- Shift registers
- EMI reduction circuitry
- Frequency Divider circuits
- Power down protection
- Functionally equivalent to the MC10/100EL29
- Computing