Parameters |
Mount |
Surface Mount |
Package / Case |
TFBGA |
Number of Pins |
68 |
JESD-609 Code |
e0 |
Pbfree Code |
no |
Number of Terminations |
68 |
Terminal Finish |
TIN LEAD |
Max Operating Temperature |
85°C |
Min Operating Temperature |
0°C |
Additional Feature |
YES |
HTS Code |
8542.39.00.01 |
Subcategory |
Programmable Logic Devices |
Technology |
CMOS |
Terminal Position |
BOTTOM |
Terminal Form |
BALL |
Peak Reflow Temperature (Cel) |
235 |
Supply Voltage |
1.8V |
Terminal Pitch |
0.5mm |
Time@Peak Reflow Temperature-Max (s) |
30 |
Pin Count |
68 |
Qualification Status |
Not Qualified |
Supply Voltage-Max (Vsup) |
1.89V |
Power Supplies |
1.2/3.31.8V |
Temperature Grade |
OTHER |
Supply Voltage-Min (Vsup) |
1.71V |
Number of I/O |
52 |
Clock Frequency |
118.3MHz |
Propagation Delay |
14 ns |
Programmable Logic Type |
FLASH PLD |
Number of Logic Blocks (LABs) |
160 |
Output Function |
MACROCELL |
Number of Macro Cells |
128 |
JTAG BST |
YES |
In-System Programmable |
YES |
Height Seated (Max) |
1.2mm |
Length |
5mm |
Width |
5mm |
RoHS Status |
RoHS Compliant |
5M160ZM68C5 Overview
This network has 128macro cells, which are cells that provide radio coverage provided by a high-power cell site (tower, antenna, mast).The product is contained in a TFBGA package.In this case, there are 52 I/Os programmed.There are 68 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line.Its terminal position is BOTTOM.A voltage of 1.8V is used as the power supply for this device.This part is part of the family [0].Chips are programmed with 68 pins.It is also characterized by YES.This electronic part is mounted in the way of Surface Mount.The device is designed with pins [0].There is 1.2/3.31.8V power supply available for it.There is a maximum supply voltage (Vsup) of 1.89V.It is recommended that the operating temperature be higher than 0°C.The operating temperature should be lower than 85°C.There are 160logic blocks (LABs) that make up its basic building block.It is important that the supply voltage (Vsup) exceeds 1.71VV.clock frequency should not exceed [0].It is possible to classify programmable logic as FLASH PLD.
5M160ZM68C5 Features
TFBGA package
52 I/Os
68 pin count
68 pins
1.2/3.31.8V power supplies
160 logic blocks (LABs)
5M160ZM68C5 Applications
There are a lot of Altera 5M160ZM68C5 CPLDs applications.
- Storage Cards and Storage Racks
- High speed graphics processing
- Complex programmable logic devices
- Voltage level translation
- POWER-SAVING MODES
- Power up sequencing
- Handheld digital devices
- Interface bridging
- Multiple Clock Source Selection
- Parity generators