NC7SZ374P6
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 6-TSSOP, SC-88, SOT-363 |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 7SZ |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 6 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | CMOS |
| Voltage - Supply | 1.65V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 1.8V |
| Terminal Pitch | 0.65mm |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| JESD-30 Code | R-PDSO-G6 |
| Function | Standard |
| Qualification Status | COMMERCIAL |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Number of Ports | 2 |
| Number of Bits | 1 |
| Clock Frequency | 175MHz |
| Family | LVC/LCX/Z |
| Current - Quiescent (Iq) | 1μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 32mA 32mA |
| Output Polarity | TRUE |
| Max Propagation Delay @ V, Max CL | 4ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3pF |
| Length | 2mm |
| RoHS Status | ROHS3 Compliant |
NC7SZ374P6 Overview
The package is in the form of 6-TSSOP, SC-88, SOT-363. D flip flop is embedded in the Tape & Reel (TR) package. There is a Tri-State, Non-Invertedoutput configured with it. The trigger configured with it uses Positive Edge. There is an electronic component mounted in the way of Surface Mount. A voltage of 1.65V~5.5Vis required for its operation. It is at -40°C~85°C TAdegrees Celsius that the system is operating. This logic flip flop is classified as type D-Type. JK flip flop is a part of the 7SZseries of FPGAs. You should not exceed 175MHzin its output frequency. A total of 1elements are present in it. There is a consumption of 1μAof quiescent energy. A total of 6 terminations have been made. A voltage of 1.8V is used as the power supply for this D latch. A JK flip flop with a 3pFfarad input capacitance is used here. LVC/LCX/Zis the family of this D flip flop. It is designed with a number of bits of 1. It reaches 5.5Vwhen the supply voltage is maximal (Vsup). This flip flop has a total of 2ports.
NC7SZ374P6 Features
Tape & Reel (TR) package
7SZ series
1 Bits
NC7SZ374P6 Applications
There are a lot of Rochester Electronics, LLC NC7SZ374P6 Flip Flops applications.
- QML qualified product
- ESCC
- Communications
- Automotive
- ATE
- Set-reset capability
- Latch-up performance
- Count Modes
- Reduced system switching noise
- Individual Asynchronous Resets