| Parameters |
| Mounting Type |
Surface Mount |
| Package / Case |
20-LCC (J-Lead) |
| Surface Mount |
YES |
| Operating Temperature |
0°C~75°C TA |
| Packaging |
Tube |
| Series |
10H |
| JESD-609 Code |
e0 |
| Pbfree Code |
no |
| Part Status |
Obsolete |
| Moisture Sensitivity Level (MSL) |
3 (168 Hours) |
| Number of Terminations |
20 |
| Type |
D-Type |
| Terminal Finish |
TIN LEAD |
| Technology |
ECL |
| Voltage - Supply |
-4.9V~-5.46V |
| Terminal Position |
QUAD |
| Terminal Form |
J BEND |
| Peak Reflow Temperature (Cel) |
240 |
| Time@Peak Reflow Temperature-Max (s) |
30 |
| JESD-30 Code |
S-PQCC-J20 |
| Function |
Reset |
| Qualification Status |
COMMERCIAL |
| Output Type |
Non-Inverted |
| Number of Elements |
1 |
| Clock Frequency |
250MHz |
| Family |
10H |
| Current - Quiescent (Iq) |
110mA |
| Output Characteristics |
OPEN-EMITTER |
| Output Polarity |
TRUE |
| Number of Bits per Element |
6 |
| Trigger Type |
Positive Edge |
| Propagation Delay (tpd) |
3 ns |
| fmax-Min |
250 MHz |
| Height Seated (Max) |
4.57mm |
| RoHS Status |
Non-RoHS Compliant |
MC10H186FN Overview
The package is in the form of 20-LCC (J-Lead). It is included in the package Tube. The output it is configured with uses Non-Inverted. Positive Edgeis the trigger it is configured with. In this case, the electronic component is mounted in the way of Surface Mount. Powered by a -4.9V~-5.46Vvolt supply, it operates as follows. Currently, the operating temperature is 0°C~75°C TA. Logic flip flops of this type are classified as D-Type. The 10Hseries comprises this type of FPGA. You should not exceed 250MHzin the output frequency of the device. D latch consists of 1 elements. As a result, it consumes 110mA of quiescent current without being affected by external factors. It has been determined that there have been 20 terminations. It is a member of the 10Hfamily of D flip flop.
MC10H186FN Features
Tube package
10H series
MC10H186FN Applications
There are a lot of Rochester Electronics, LLC MC10H186FN Flip Flops applications.
- Bus hold
- Digital electronics systems
- Asynchronous counter
- Common Clocks
- Bounce elimination switch
- Patented noise
- CMOS Process
- Convert a momentary switch to a toggle switch
- Reduced system switching noise
- Parallel data storage