A2F500M3G-PQ208
| Parameters | |
|---|---|
| Factory Lead Time | 12 Weeks |
| Package / Case | 208-BFQFP |
| Surface Mount | YES |
| Number of Pins | 208 |
| Operating Temperature | 0°C~85°C TJ |
| Packaging | Tray |
| Published | 2015 |
| Series | SmartFusion® |
| JESD-609 Code | e0 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 208 |
| Terminal Finish | Tin/Lead (Sn/Pb) |
| HTS Code | 8542.39.00.01 |
| Technology | CMOS |
| Terminal Position | QUAD |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 225 |
| Supply Voltage | 1.5V |
| Terminal Pitch | 0.5mm |
| Frequency | 80MHz |
| Time@Peak Reflow Temperature-Max (s) | 20 |
| Base Part Number | A2F500M3G |
| Supply Voltage-Max (Vsup) | 1.575V |
| Supply Voltage-Min (Vsup) | 1.425V |
| Interface | Ethernet, I2C, SPI, UART, USART |
| Number of I/O | MCU - 22, FPGA - 66 |
| RAM Size | 64KB |
| Core Processor | ARM® Cortex®-M3 |
| Peripherals | DMA, POR, WDT |
| Connectivity | Ethernet, I2C, SPI, UART/USART |
| Architecture | MCU, FPGA |
| Organization | 11520 CLBS, 500000 GATES |
| Programmable Logic Type | FIELD PROGRAMMABLE GATE ARRAY |
| Core Architecture | ARM |
| Number of Logic Blocks (LABs) | 24 |
| Primary Attributes | ProASIC®3 FPGA, 500K Gates, 11520 D-Flip-Flops |
| Number of Equivalent Gates | 500000 |
| Flash Size | 512KB |
| Height Seated (Max) | 4.1mm |
| Length | 28mm |
| Width | 28mm |
| RoHS Status | Non-RoHS Compliant |
This SoC is built on ARM? Cortex?-M3 core processor(s).
A core processor ARM? Cortex?-M3 is embedded in this SoC.There is a 208-BFQFP package assigned to this system on a chip by the manufacturer.With 64KB RAM implemented, this SoC chip provides users with a high level of performance.The internal architecture of this SoC design is based on the MCU, FPGA technique.It is part of the SmartFusion? series of system on a chips.Temperatures should be 0°C~85°C TJ on average for this SoC meaning.This SoC security combines ProASIC?3 FPGA, 500K Gates, 11520 D-Flip-Flops, an important feature to keep in mind.Tray package houses this SoC system on a chip.MCU - 22, FPGA - 66 I/Os are available in this SoC part.It is recommended to use a 1.5V power supply.There are voltages higher than 1.575V that should be avoided when using the SoCs wireless.There is a possibility that it can be powered by a power supply of at least 1.425V.You can reconfigure FIELD PROGRAMMABLE GATE ARRAY to meet your specific design needs.There are 208 terminations in total and that really benefits system on a chip.This flash has a size of 512KB.Searching A2F500M3G will bring up system on chips with similar specs and purposes.During operation, the wireless SoC runs at a frequency of 80MHz.There are a number of features to this SoC meaning which are based on the core architecture of ARM.208 pins are present on this computer SoC.
ARM? Cortex?-M3 processor.
64KB RAM.
Built on MCU, FPGA.
512KB extended flash.
Core Architecture: ARM
There are a lot of Microsemi Corporation
A2F500M3G-PQ208 System On Chip (SoC) applications.
- External USB hard disk/SSD
- Industrial robot
- Industrial Pressure
- Networked sensors
- Central inverter
- Embedded systems
- AC drive control module
- RISC-V
- Communication network-on-Chip (cNoC)
- ARM Cortex M4 microcontroller