74LVTH16374MTD
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 48-TFSOP (0.240, 6.10mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74LVTH |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 2 (1 Year) |
| Number of Terminations | 48 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.5mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Function | Standard |
| Qualification Status | COMMERCIAL |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Number of Ports | 2 |
| Clock Frequency | 160MHz |
| Family | LVT |
| Current - Quiescent (Iq) | 190μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 32mA 64mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 4.5ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4pF |
| Width | 6.1mm |
| RoHS Status | ROHS3 Compliant |
74LVTH16374MTD Overview
The item is packaged in 48-TFSOP (0.240, 6.10mm Width)cases. The package Tubecontains it. T flip flop uses Tri-State, Non-Invertedas its output configuration. JK flip flop uses Positive Edgeas the trigger. Surface Mountis in the way of this electric part. A voltage of 2.7V~3.6Vis required for its operation. In the operating environment, the temperature is -40°C~85°C TA. This D latch has the type D-Type. It belongs to the 74LVTHseries of FPGAs. You should not exceed 160MHzin the output frequency of the device. D latch consists of 2 elements. As a result, it consumes 190μA of quiescent current without being affected by external factors. It has been determined that there have been 48 terminations. The D flip flop is powered by a voltage of 3.3V . A JK flip flop with a 4pFfarad input capacitance is used here. It belongs to the family of electronic devices known as LVT. As soon as Vsup reaches 3.6V, the maximum supply voltage is reached. This D flip flop is equipped with 0 ports.
74LVTH16374MTD Features
Tube package
74LVTH series
74LVTH16374MTD Applications
There are a lot of Rochester Electronics, LLC 74LVTH16374MTD Flip Flops applications.
- Counters
- Event Detectors
- Balanced Propagation Delays
- Guaranteed simultaneous switching noise level
- Instrumentation
- Power down protection
- Balanced 24 mA output drivers
- Computing
- Single Down Count-Control Line
- Automotive