74LVT374MTCX
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-TSSOP (0.173, 4.40mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVT |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | BICMOS |
| Voltage - Supply | 2.7V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 3.3V |
| Terminal Pitch | 0.65mm |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 2.7V |
| Number of Ports | 2 |
| Clock Frequency | 160MHz |
| Family | LVT |
| Current - Quiescent (Iq) | 190μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 32mA 64mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 4.9ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3pF |
| Propagation Delay (tpd) | 5.2 ns |
| Length | 6.5mm |
| Width | 4.4mm |
| RoHS Status | ROHS3 Compliant |
74LVT374MTCX Overview
In the form of 20-TSSOP (0.173, 4.40mm Width), it has been packaged. As part of the package Tape & Reel (TR), it is embedded. In the configuration, Tri-State, Non-Invertedis used as the output. There is a trigger configured with Positive Edge. In this case, the electronic component is mounted in the way of Surface Mount. The supply voltage is set to 2.7V~3.6V. It is operating at a temperature of -40°C~85°C TA. It is an electronic flip flop with the type D-Type. The FPGA belongs to the 74LVT series. It should not exceed 160MHzin its output frequency. A total of 1elements are contained within it. T flip flop consumes 190μA quiescent energy. It has been determined that there have been 20 terminations. A voltage of 3.3V is used to power it. Its input capacitance is 3pFfarads. It is a member of the LVTfamily of D flip flop. Vsup reaches its maximum value at 3.6V. For normal operation, the supply voltage (Vsup) should be above 2.7V. The D flip flop is embedded with 2ports.
74LVT374MTCX Features
Tape & Reel (TR) package
74LVT series
74LVT374MTCX Applications
There are a lot of Rochester Electronics, LLC 74LVT374MTCX Flip Flops applications.
- Differential Individual
- Registers
- Bus hold
- Single Up Count-Control Line
- Memory
- Common Clocks
- ESD protection
- ESCC
- Data transfer
- Data storage