74LVQ374QSC
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 20-LSSOP (0.154, 3.90mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74LVQ |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 20 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | CMOS |
| Voltage - Supply | 2V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.7V |
| Terminal Pitch | 0.635mm |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| JESD-30 Code | R-PDSO-G20 |
| Function | Standard |
| Qualification Status | COMMERCIAL |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Supply Voltage-Min (Vsup) | 2V |
| Number of Ports | 2 |
| Clock Frequency | 75MHz |
| Family | LVQ |
| Current - Quiescent (Iq) | 40μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 12mA 12mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 8 |
| Max Propagation Delay @ V, Max CL | 13ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4.5pF |
| RoHS Status | ROHS3 Compliant |
74LVQ374QSC Overview
The package is in the form of 20-LSSOP (0.154, 3.90mm Width). Package Tubeembeds it. As configured, the output uses Tri-State, Non-Inverted. It is configured with a trigger that uses a value of Positive Edge. This electronic part is mounted in the way of Surface Mount. A voltage of 2V~3.6Vis required for its operation. Currently, the operating temperature is -40°C~85°C TA. Logic flip flops of this type are classified as D-Type. It belongs to the 74LVQseries of FPGAs. It should not exceed 75MHzin its output frequency. D latch consists of 1 elements. There is 40μA quiescent consumption. 20terminations have occurred. Power is supplied from a voltage of 2.7V volts. JK flip flop input capacitance is 4.5pF farads. LVQis the family of this D flip flop. It reaches the maximum supply voltage (Vsup) at 3.6V. Keeping the supply voltage (Vsup) above 2V is necessary for normal operation. A D flip flop with 2embedded ports is available.
74LVQ374QSC Features
Tube package
74LVQ series
74LVQ374QSC Applications
There are a lot of Rochester Electronics, LLC 74LVQ374QSC Flip Flops applications.
- Modulo – n – counter
- Computing
- Buffer registers
- Event Detectors
- Reduced system switching noise
- Data Synchronizers
- Data transfer
- Frequency Dividers
- Individual Asynchronous Resets
- Balanced Propagation Delays