74LVC821AD,118
| Parameters | |
|---|---|
| Current - Quiescent (Iq) | 10μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Max I(ol) | 0.024 A |
| Number of Bits per Element | 10 |
| Max Propagation Delay @ V, Max CL | 7.3ns @ 3.3V, 50pF |
| Prop. Delay@Nom-Sup | 9.5 ns |
| Trigger Type | Positive Edge |
| Input Capacitance | 5pF |
| Height Seated (Max) | 2.65mm |
| Width | 7.5mm |
| RoHS Status | ROHS3 Compliant |
| Mounting Type | Surface Mount |
| Package / Case | 24-SOIC (0.295, 7.50mm Width) |
| Surface Mount | YES |
| Operating Temperature | -40°C~125°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74LVC |
| JESD-609 Code | e4 |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 24 |
| Type | D-Type |
| Terminal Finish | NICKEL PALLADIUM GOLD |
| Subcategory | FF/Latches |
| Packing Method | TAPE AND REEL |
| Technology | CMOS |
| Voltage - Supply | 1.65V~3.6V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 2.7V |
| Time@Peak Reflow Temperature-Max (s) | 30 |
| Base Part Number | 74LVC821 |
| JESD-30 Code | R-PDSO-G24 |
| Function | Standard |
| Qualification Status | Not Qualified |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 3.6V |
| Power Supplies | 3.3V |
| Load Capacitance | 50pF |
| Number of Ports | 2 |
| Clock Frequency | 200MHz |
| Family | LVC/LCX/Z |
74LVC821AD,118 Overview
The flip flop is packaged in a case of 24-SOIC (0.295, 7.50mm Width). It is contained within the Tape & Reel (TR)package. T flip flop uses Tri-State, Non-Invertedas the output. In the configuration of the trigger, Positive Edgeis used. Surface Mountis occupied by this electronic component. With a supply voltage of 1.65V~3.6V volts, it operates. It is operating at a temperature of -40°C~125°C TA. D-Typeis the type of this D latch. It belongs to the 74LVCseries of FPGAs. A frequency of 200MHzshould not be exceeded by its output. In total, there are 1 elements. It consumes 10μA of quiescent A total of 24 terminations have been made. The 74LVC821 family contains this object. The D flip flop is powered by a voltage of 2.7V . JK flip flop input capacitance is 5pF farads. It is a member of the LVC/LCX/Zfamily of D flip flop. The part is included in FF/Latches. Vsup reaches 3.6V, the maximal supply voltage. Compared to other similar T flip flops, this device offers reliable performance and is well suited for TAPE AND REEL. A total of 3.3V power supplies are needed to run it. The flip flop has 2embedded ports.
74LVC821AD,118 Features
Tape & Reel (TR) package
74LVC series
3.3V power supplies
74LVC821AD,118 Applications
There are a lot of NXP USA Inc. 74LVC821AD,118 Flip Flops applications.
- Shift registers
- Data storage
- ESD performance
- Buffered Clock
- Storage Registers
- Memory
- Dynamic threshold performance
- Patented noise
- Frequency Divider circuits
- Counters