74F112SJX
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC (0.209, 5.30mm Width) |
| Surface Mount | YES |
| Operating Temperature | 0°C~70°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74F |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Number of Terminations | 16 |
| Type | JK Type |
| Terminal Finish | MATTE TIN |
| Technology | TTL |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Terminal Form | GULL WING |
| Peak Reflow Temperature (Cel) | 260 |
| Supply Voltage | 5V |
| Reach Compliance Code | unknown |
| Time@Peak Reflow Temperature-Max (s) | NOT SPECIFIED |
| Function | Set(Preset) and Reset |
| Qualification Status | Not Qualified |
| Output Type | Differential |
| Number of Elements | 2 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Clock Frequency | 105MHz |
| Family | F/FAST |
| Current - Quiescent (Iq) | 19mA |
| Current - Output High, Low | 1mA 20mA |
| Output Polarity | COMPLEMENTARY |
| Number of Bits per Element | 1 |
| Max Propagation Delay @ V, Max CL | 6.5ns @ 5V, 50pF |
| Trigger Type | Negative Edge |
| Propagation Delay (tpd) | 7.5 ns |
| fmax-Min | 80 MHz |
| Width | 5.3mm |
| RoHS Status | ROHS3 Compliant |
74F112SJX Overview
It is embeded in 16-SOIC (0.209, 5.30mm Width) case. The package Tape & Reel (TR)contains it. It is configured with Differentialas an output. JK flip flop uses Negative Edgeas the trigger. It is mounted in the way of Surface Mount. A voltage of 4.5V~5.5Vis required for its operation. The operating temperature is 0°C~70°C TA. This logic flip flop is classified as type JK Type. JK flip flop is a part of the 74Fseries of FPGAs. A frequency of 105MHzshould not be exceeded by its output. D latch consists of 2 elements. Despite external influences, it consumes 19mAof quiescent current. Terminations are 16. The power supply voltage is 5V. F/FASTis the family of this D flip flop. 5.5Vis the maximum supply voltage (Vsup). Normally, the supply voltage (Vsup) should be above 4.5V.
74F112SJX Features
Tape & Reel (TR) package
74F series
74F112SJX Applications
There are a lot of Rochester Electronics, LLC 74F112SJX Flip Flops applications.
- Power down protection
- High Performance Logic for test systems
- QML qualified product
- Computers
- Matched Rise and Fall
- EMI reduction circuitry
- Supports Live Insertion
- Event Detectors
- Bounce elimination switch
- Memory