74ALVT16821DGG,118
| Parameters | |
|---|---|
| Mounting Type | Surface Mount |
| Package / Case | 56-TFSOP (0.240, 6.10mm Width) |
| Supplier Device Package | 56-TSSOP |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tape & Reel (TR) |
| Series | 74ALVT |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 1 (Unlimited) |
| Type | D-Type |
| Voltage - Supply | 2.3V~2.7V 3V~3.6V |
| Function | Standard |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 2 |
| Clock Frequency | 150MHz |
| Current - Quiescent (Iq) | 70μA |
| Current - Output High, Low | 8mA 24mA; 32mA 64mA |
| Number of Bits per Element | 10 |
| Max Propagation Delay @ V, Max CL | 3.2ns @ 3.3V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 3pF |
| RoHS Status | ROHS3 Compliant |
74ALVT16821DGG,118 Overview
The flip flop is packaged in a case of 56-TFSOP (0.240, 6.10mm Width). Package Tape & Reel (TR)embeds it. Currently, the output is configured to use Tri-State, Non-Inverted. This trigger uses the value Positive Edge. Surface Mountis positioned in the way of this electronic part. A voltage of 2.3V~2.7V 3V~3.6Vis required for its operation. Temperature is set to -40°C~85°C TA. The type of this D latch is D-Type. The FPGA belongs to the 74ALVT series. In order for it to function properly, its output frequency should not exceed 150MHz. D latch consists of 2 elements. As a result, it consumes 70μA of quiescent current without being affected by external factors. The input capacitance of this JK flip flopis 3pF farads.
74ALVT16821DGG,118 Features
Tape & Reel (TR) package
74ALVT series
74ALVT16821DGG,118 Applications
There are a lot of Rochester Electronics, LLC 74ALVT16821DGG,118 Flip Flops applications.
- Latch-up performance
- QML qualified product
- ESCC
- ESD performance
- Data transfer
- Digital electronics systems
- Parallel data storage
- Latch
- Communications
- Instrumentation