74ACTQ821SPC
| Parameters | |
|---|---|
| Mounting Type | Through Hole |
| Package / Case | 24-DIP (0.300, 7.62mm) |
| Surface Mount | NO |
| Operating Temperature | -40°C~85°C TA |
| Packaging | Tube |
| Series | 74ACTQ |
| JESD-609 Code | e3 |
| Pbfree Code | yes |
| Part Status | Obsolete |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| Number of Terminations | 24 |
| Type | D-Type |
| Terminal Finish | MATTE TIN |
| Technology | CMOS |
| Voltage - Supply | 4.5V~5.5V |
| Terminal Position | DUAL |
| Peak Reflow Temperature (Cel) | NOT APPLICABLE |
| Supply Voltage | 5V |
| Terminal Pitch | 2.54mm |
| Time@Peak Reflow Temperature-Max (s) | NOT APPLICABLE |
| JESD-30 Code | R-PDIP-T24 |
| Function | Standard |
| Qualification Status | COMMERCIAL |
| Output Type | Tri-State, Non-Inverted |
| Number of Elements | 1 |
| Supply Voltage-Max (Vsup) | 5.5V |
| Supply Voltage-Min (Vsup) | 4.5V |
| Number of Ports | 2 |
| Clock Frequency | 120MHz |
| Family | ACT |
| Current - Quiescent (Iq) | 80μA |
| Output Characteristics | 3-STATE |
| Current - Output High, Low | 24mA 24mA |
| Output Polarity | TRUE |
| Number of Bits per Element | 10 |
| Max Propagation Delay @ V, Max CL | 9.5ns @ 5V, 50pF |
| Trigger Type | Positive Edge |
| Input Capacitance | 4.5pF |
| Height Seated (Max) | 5.08mm |
| Width | 7.62mm |
| RoHS Status | ROHS3 Compliant |
74ACTQ821SPC Overview
As a result, it is packaged as 24-DIP (0.300, 7.62mm). D flip flop is embedded in the Tube package. T flip flop uses Tri-State, Non-Invertedas its output configuration. Positive Edgeis the trigger it is configured with. Through Holeis in the way of this electric part. A supply voltage of 4.5V~5.5V is required for operation. The operating temperature is -40°C~85°C TA. D-Typeis the type of this D latch. The 74ACTQseries comprises this type of FPGA. There should be no greater frequency than 120MHzon its output. In total, it contains 1 elements. T flip flop consumes 80μA quiescent energy. There are 24 terminations,It is powered from a supply voltage of 5V. This JK flip flop has a 4.5pFfarad input capacitance. Electronic devices of this type belong to the ACTfamily. In this case, the maximum supply voltage (Vsup) reaches 5.5V. A normal operating voltage (Vsup) should remain above 4.5V. There are 2 terminations, which are the practice of ending a transmission line with a device that matches the characteristic impedance of the line.
74ACTQ821SPC Features
Tube package
74ACTQ series
74ACTQ821SPC Applications
There are a lot of Rochester Electronics, LLC 74ACTQ821SPC Flip Flops applications.
- CMOS Process
- Storage Registers
- Counters
- Communications
- High Performance Logic for test systems
- ESD protection
- Computing
- Synchronous counter
- Balanced 24 mA output drivers
- Supports Live Insertion